PIC16LF818-I/SO Microchip Technology, PIC16LF818-I/SO Datasheet - Page 28

IC MCU FLASH 1KX14 EEPROM 18SOIC

PIC16LF818-I/SO

Manufacturer Part Number
PIC16LF818-I/SO
Description
IC MCU FLASH 1KX14 EEPROM 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16LF818-I/SO

Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Controller Family/series
PIC16LF
No. Of I/o's
16
Eeprom Memory Size
128Byte
Ram Memory Size
128Byte
Cpu Speed
20MHz
No. Of Timers
3
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
I2C, SPI, SSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
1 x 16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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PIC16F818/819
REGISTER 3-1:
DS39598E-page 26
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
EECON1: EEPROM ACCESS CONTROL REGISTER 1 (ADDRESS 18Ch)
bit 7
EEPGD: Program/Data EEPROM Select bit
1 = Accesses program memory
0 = Accesses data memory
Reads ‘0’ after a POR; this bit cannot be changed while a write operation is in progress.
Unimplemented: Read as ‘0’
FREE: EEPROM Forced Row Erase bit
1 = Erase the program memory row addressed by EEADRH:EEADR on the next WR command
0 = Perform write-only
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during normal
0 = The write operation completed
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
WR: Write Control bit
1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit
0 = Write cycle to the EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read, RD is cleared in hardware. The RD bit can only be set (not
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit
-n = Value at POR
EEPGD
R/W-x
operation)
can only be set (not cleared) in software.
cleared) in software.
U-0
W = Writable bit
‘1’ = Bit is set
U-0
R/W-x
FREE
S = Set only
‘0’ = Bit is cleared
WRERR
R/W-x
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
WREN
R/W-0
 2004 Microchip Technology Inc.
R/S-0
WR
R/S-0
RD
bit 0

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