PIC24FJ32GA002-I/SO Microchip Technology, PIC24FJ32GA002-I/SO Datasheet - Page 45

• Manufacturer Part Number: PIC24FJ32GA002-I/SO
• Description: IC PIC MCU FLASH 11KX24 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ32GA002-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 32KB (11K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DM300027, DV164033, MA240013, AC164127, DM240002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Controller Family/series: PIC24
• No. Of I/o's: 21
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164339 - MODULE SKT FOR PM3 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.4.2
After
programmed to executive memory using ICSP, it must
be verified. Verification is performed by reading out the
contents of executive memory and comparing it with
the image of the programming executive stored in the
programmer.
TABLE 5-6:
© 2008 Microchip Technology Inc.
Step 1: Exit the Reset vector.
Step 2: Initialize TBLPAG and the Read Pointer (W6) for TBLRD instruction.
Step 3: Initialize the Write Pointer (W7) to point to the VISI register.
Step 4: Read and clock out the contents of the next two locations of executive memory through the VISI register
Step 5: Reset the device internal PC.
Step 6: Repeat Steps 4 and 5 until all desired code memory is read.
Command
(Binary)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0000
0000
0000
0000
0000
0000
0000
0001
0000
0000
0000
0000
0001
0000
0000
0000
the
using the REGOUT command.
PROGRAMMING VERIFICATION
programming
READING EXECUTIVE MEMORY
000000
040200
000000
200800
880190
EB0300
207847
000000
BA0B96
000000
000000
<VISI>
000000
BADBB6
000000
000000
BAD3D6
000000
000000
<VISI>
000000
BA0BB6
000000
000000
<VISI>
000000
040200
000000
(Hex)
Data
executive
NOP
GOTO
NOP
MOV
MOV
CLR
MOV
NOP
TBLRDL
NOP
NOP
Clock out contents of VISI register
NOP
TBLRDH.B [W6++], [W7++]
NOP
NOP
TBLRDH.B [++W6], [W7--]
NOP
NOP
Clock out contents of VISI register
NOP
TBLRDL
NOP
NOP
Clock out contents of VISI register
NOP
GOTO
NOP
0x200
#0x80, W0
W0, TBLPAG
W6
#VISI, W7
[W6], [W7]
[W6++], [W7]
0x200
has
been
Reading the contents of executive memory can be
performed using the same technique described in
Section 3.8 “Reading Code Memory”. A procedure
for reading executive memory is shown in Table 5-6.
Note that in Step 2, the TBLPAG register is set to 80h,
such that executive memory may be read. The last
eight words of executive memory should be verified
with stored values of the Diagnostic and Calibration
Words to ensure accuracy.
PIC24FJXXXGA0XX
Description
DS39768D-page 45