PIC24HJ12GP201-I/P Microchip Technology, PIC24HJ12GP201-I/P Datasheet - Page 2

• Manufacturer Part Number: PIC24HJ12GP201-I/P
• Description: IC PIC MCU FLASH 4KX24 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ12GP201-I/P

• Program Memory Type: FLASH
• Program Memory Size: 12KB (4K x 24)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit or 6-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164337 - MODULE SOCKET FOR PM3 40DIP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 2:
DS80466E-page 2
Note 1:
PSV Oper-
Controller
Identifica-
Regulator
Interrupt
Module
Product
Internal
Voltage
UART
UART
UART
UART
UART
UART
UART
UART
UART
ations
JTAG
I
2
SPI
tion
I
I
C™
2
2
C
C
Only those issues indicated in the last column apply to the current silicon revision.
Programming
Temperature
Sleep Mode
High-Speed
High-Speed
High-Speed
SFR Writes
Addressing
Addressing
SCKx Pins
Auto-Baud
Auto-Baud
Auto-Baud
Idle Mode
Extended
Interrupts
IR Mode
IR Mode
SILICON ISSUE SUMMARY
Feature
Flash
Mode
Mode
Mode
10-bit
10-bit
—
Number
Item
10.
12.
13.
14.
15.
16.
17.
18.
11.
1.
2.
3.
4.
5.
6.
7.
8.
9.
JTAG programming does not work.
UART receptions may be corrupted if the Baud Rate
Generator (BRG) is set up for 4x mode.
The auto-baud feature may not calculate the correct baud
rate when the BRG is set up for 4x mode.
With the auto-baud feature selected, the Sync Break
character (0x55) may be loaded into the FIFO as data.
The auto-baud feature measures baud rate inaccurately for
certain baud rate and clock speed combinations.
When an auto-baud is detected, the receive interrupt may
occur twice.
When the UART is in 4x mode (BRGH = 1) and using two
Stop bits (STSEL = 1), it may sample the first Stop bit
instead of the second one.
The 16x baud clock signal on the BCLK pin is present only
when the module is transmitting.
If a clock failure occurs when the device is in Idle mode,
the oscillator failure trap does not vector to the Trap
Service Routine (TSR).
The SPIxCON1 DISSCK bit does not influence port
functionality.
The BCL bit in I2CSTAT can only be cleared with a 16-bit
operation, and can be corrupted with 1-bit or 8-bit
operations on I2CSTAT.
When the I
using the same address bits (A10 and A9) as other I
devices, the A10 and A9 bits may not work as expected.
Revision A2 devices marked as extended temperature
range (E) devices only support industrial temperature
range (I).
The UART error interrupt may not occur, or may occur at
an incorrect time, if multiple errors occur during a short
period of time.
When the UART module is operating in 8-bit mode (PDSEL
= 0x) and using the IrDA
module incorrectly transmits a data payload of 80h as 00h.
When the VREGS bit (RCON<8>) is set to a logic ‘0’,
device may Reset and higher sleep current may be
observed.
An address error trap occurs in certain addressing modes
when accessing the first four bytes of any PSV page.
When the I
an address of 0x102, the I2CxRCV register content for the
lower address byte is 0x01 rather than 0x02.
2
2
C module is configured for 10-bit addressing
C module is configured as a 10-bit slave with
Issue Summary
®
encoder/decoder (IREN = 1), the
© 2010 Microchip Technology Inc.
2
C
A2 A3 A4 A5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Revisions
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X