PIC18LF25J50-I/SP Microchip Technology, PIC18LF25J50-I/SP Datasheet - Page 3

• Manufacturer Part Number: PIC18LF25J50-I/SP
• Description: IC PIC MCU FLASH 32K 2V 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF25J50-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 16
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 31 KHz
• Number Of Programmable I/os: 16
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180024
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Silicon Errata Issues
1. Module: Master Synchronous Serial Port
 2010 Microchip Technology Inc.
Note:
If the LATB<5> or LATB<4> bit is set, the
MSSP1 module will not work correctly in the
I
are clear, the module will work normally.
Work around
Clear the bits, LATB<5:4>, prior to enabling the
MSSP1 module in an I
clear while using the module.
For operation in I
bits should be set.
Affected Silicon Revisions
2
C™ modes. If both LATB<5> and LATB<4>
A2
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (Rev. A4).
A4
(MSSP1)
2
C modes, the TRISB<5:4>
2
C mode. Keep these bits
PIC18F46J50 FAMILY
2. Module: Master Synchronous Serial Port
In extremely rare cases, when configured for I
slave reception, the MSSP module may not receive
the correct data. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPxBUF) is not
read within a window after the SSPxIF interrupt
has occurred.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
• Each time the SSPxIF is set, read the
Affected Silicon Revisions
A2
clock stretching feature.
This
(SSPxCON2<0>).
SSPxBUF before the first rising clock edge of
the next byte being received.
X
A4
X
is
(MSSP)
done
2
C slave reception, enable the
by
setting
DS80436C-page 3
the
SEN
2
C™
bit