PIC18F45J50-I/PT Microchip Technology, PIC18F45J50-I/PT Datasheet
PIC18F45J50-I/PT
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PIC18F45J50-I/PT Summary of contents
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... High-Performance USB Microcontrollers © 2009 Microchip Technology Inc. PIC18F46J50 Family 28/44-Pin, Low-Power, with nanoWatt XLP Technology Data Sheet DS39931C ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Secondary Oscillator using Timer1 @ 32 kHz • Fail-Safe Clock Monitor: - Allows for safe shutdown if any clock stops • Two-Speed Oscillator Start-up • Programmable Reference Clock Output Generator © 2009 Microchip Technology Inc. Peripheral Highlights: • Peripheral Pin Select: - Allows independent I/O mapping of many peripherals ...
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... PIC18F46J50 FAMILY (1) PIC18F/LF Device PIC18F24J50 28 16K 3776 16 PIC18F25J50 28 32K 3776 16 PIC18F26J50 28 64K 3776 16 PIC18F44J50 44 16K 3776 22 PIC18F45J50 44 32K 3776 22 PIC18F46J50 44 64K 3776 22 PIC18LF24J50 28 16K 3776 16 28 32K 3776 16 PIC18LF25J50 28 64K 3776 16 PIC18LF26J50 44 16K 3776 22 PIC18LF44J50 44 32K 3776 22 PIC18LF45J50 44 64K 3776 22 PIC18LF46J50 Note 1: See Section 1.3 “ ...
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... Table 9-14, respectively. For details on configuring the PPS module, see Section 9.7 “Peripheral Pin Select (PPS)”. 2: See Section 26.3 “On-Chip Voltage Regulator” for details on how to connect the V 3: For the QFN package recommended that the bottom pad be connected to V © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY ...
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... See Section 26.3 “On-Chip Voltage Regulator” for details on how to connect the V 3: For the QFN package recommended that the bottom pad be connected to V DS39931C-page PIC18F4XJ50 Pins are up to 5.5V tolerant OSC2/CLKO/RA6 OSC1/CLKI/RA7 RE2/AN7/PMCS RE1/AN6/PMWR RE0/AN5/PMRD RA5/AN4/SS1/HLVDIN/RCV/RP2 ( DDCORE CAP /V pin. DDCORE CAP . SS © 2009 Microchip Technology Inc. ...
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... RPn pins. For a list of the input and output functions, see Table 9-13 and Table 9-14, respectively. For details on configuring the PPS module, see Section 9.7 “Peripheral Pin Select (PPS)”. 2: See Section 26.3 “On-Chip Voltage Regulator” for details on how to connect the V © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY ...
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... Electrical Characteristics .......................................................................................................................................................... 485 30.0 Packaging Information.............................................................................................................................................................. 525 Appendix A: Revision History............................................................................................................................................................. 537 Appendix B: Device Differences......................................................................................................................................................... 537 The Microchip Web Site ..................................................................................................................................................................... 551 Customer Change Notification Service .............................................................................................................................................. 551 Customer Support .............................................................................................................................................................................. 551 Reader Response .............................................................................................................................................................................. 552 Product Identification System............................................................................................................................................................. 553 DS39931C-page 8 © 2009 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY DS39931C-page 9 ...
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... PIC18F46J50 FAMILY NOTES: DS39931C-page 10 © 2009 Microchip Technology Inc. ...
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... PIC18LF24J50 • PIC18F25J50 • PIC18LF25J50 • PIC18F26J50 • PIC18LF26J50 • PIC18F44J50 • PIC18LF44J50 • PIC18F45J50 • PIC18LF45J50 • PIC18F46J50 • PIC18LF46J50 This family introduces a new line of low-voltage Universal Serial Bus (USB) microcontrollers with the main traditional advantage of all PIC18 microcontrollers, namely, high computational performance and a rich feature set at an extremely competitive price point ...
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... For “LF” parts, an external supply of 2.0V-2.7V has to be supplied to the V DDCORE 2.0V-3.6V can be supplied never exceed For more details about the internal voltage regulator, see Section 26.3 “On-Chip Voltage Regulator”. © 2009 Microchip Technology Inc. but should DD, through a SS pin while should DDCORE ...
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... MSSP (2), Enhanced USART (2), USB No 10 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set Enabled 28-Pin QFN, SOIC, SSOP and SPDIP (300 mil) PIC18F44J50 PIC18F45J50 DC – 48 MHz DC – 48 MHz 16K 32K 8,192 16,384 3.8K 3 ...
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... Power-on Reset Watchdog Timer Brown-out (2) Reset MCLR DD SS Timer1 Timer2 Timer3 Timer4 EUSART2 EUSART1 PORTA Data Latch (1) RA0:RA7 (3.8 Kbytes) 12 PORTB (1) RB0:RB7 12 4 Access Bank 12 PORTC (1) RC0:RC7 logic 8 PRODH PRODL Multiply ALU<8> 8 Comparators MSSP1 MSSP2 USB © 2009 Microchip Technology Inc. ...
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... RTCC Timer0 HLVD 10-Bit PMP CTMU ECCP1 Note 1: See Table 1-3 for I/O port pin descriptions. 2: The on-chip voltage regulator is always enabled by default. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Data Latch 8 8 Data Memory (3.8 Kbytes) PCLATU PCLATH Address Latch ...
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... In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL Digital I/O. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode C™ = Open-Drain, I Description ) specific © 2009 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Pin Buffer Type Type 28-QFN PORTA is a bidirectional I/O port. ...
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... Digital I/O. I Analog Analog input 9. I/O ST CTMU edge 2 input. O DIG External USB transceiver D+ data output. I DIG Remappable peripheral pin 6 input/output. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode C™ = Open-Drain, I Description ) specific © 2009 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Pin Buffer Type Type 28-QFN PORTB (continued) 22 ...
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... Asynchronous serial receive data input. I/O ST Synchronous serial data output/input. O DIG SPI data output. I/O DIG Remappable peripheral pin 18 input/output. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode C™ = Open-Drain, I Description ) specific © 2009 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Pin Buffer Type Type 28-QFN 5 P — ...
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... RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL Digital I/O. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode C™ = Open-Drain, I Description ) specific © 2009 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Pin Buffer 44- 44- Type Type TQFP PORTA is a bidirectional I/O port ...
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... CTMU edge 2 input. O DIG Parallel Master Port address. O DIG External USB transceiver D+ data output. I/O DIG Remappable peripheral pin 6 input/output. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode C™ = Open-Drain, I Description ) specific © 2009 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Pin Buffer 44- 44- Type Type TQFP ...
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... EUSART1 synchronous data (see related TX1/CK1). I/O ST Synchronous serial data output/input. O DIG SPI data output. I/O DIG Remappable peripheral pin 18 input/output. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode C™ = Open-Drain, I Description ) specific © 2009 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Pin Buffer 44- 44- Type Type TQFP PORTD is a bidirectional I/O port ...
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... P — Positive supply for analog modules. 28 — — — Positive supply for analog modules — USB voltage input pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode C™ = Open-Drain, I Description ) specific © 2009 Microchip Technology Inc. ...
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... RA6, the output frequency will be one fourth of the peripheral clock frequency. The clock output stops when in Sleep mode, but will continue during Idle mode (see Figure 2-1). © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY TABLE 2-1: Mode ...
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... USB Module Clock Needs 48 MHz for FS ÷ Needs 6 MHz for LS 0 ÷ CPDIV<1:0> Primary Clock IDLE (4) Source CPU 00 (3) Peripherals 01 RA6 11 ÷ 4 OSCCON<1:0> CLKO Enabled Modes WDT, PWRT, FSCM and Two-Speed Start-up to lock. During this time, the rc © 2009 Microchip Technology Inc. ...
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... See the notes following Table 2-3 for additional information. Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY TABLE 2-3: Osc Type HS Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation ...
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... Watchdog Timer • Two-Speed Start-up These features are discussed in larger detail in Section 26.0 “Special Features of the CPU”. The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (page 37). © 2009 Microchip Technology Inc. ...
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... The low-frequency INTRC oscillator operates indepen- dently of the INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 2.2.5.3 Compensating for INTOSC Drift It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register ...
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... USB operation. TABLE 2-4: CLOCK FOR LOW-SPEED USB Clock CPU CPDIV<1:0> Input Clock R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown USB Clock ‘10’ 48 MHz ‘11’ 24 MHz © 2009 Microchip Technology Inc. ...
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... All clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz). Bold text highlights the clock selections that are compatible with low-speed USB operation (system clock of 24 MHz, USB clock of 6 MHz). © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Clock Mode MCU Clock Division (FOSC< ...
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... INTRC is providing the clock or the internal oscillator block has just started and is not yet stable. The IDLEN bit determines if the device goes into Sleep mode, or one of the Idle modes, when the SLEEP instruction is executed. Oscillator Frequency Select bits, bit in the OSCTUNE register © 2009 Microchip Technology Inc. ...
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... Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 2: Default output frequency of INTOSC on Reset (4 MHz). 3: Source selected by the INTSRC bit (OSCTUNE<7>). © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 2.5.2 OSCILLATOR TRANSITIONS PIC18F46J50 Family devices contain circuitry to prevent clock “glitches” when switching between clock sources ...
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... R/W-0 R/W-0 R/W-0 ROSEL RODIV3 RODIV2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) used as the base clock; base clock reflects any clock switching of the device R/W-0 R/W-0 RODIV1 RODIV0 bit Bit is unknown (1) © 2009 Microchip Technology Inc. ...
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... Sleep mode achieves the lowest current consumption of the device (only leakage currents) outside of Deep Sleep. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Sleep mode should not be invoked while the USB module is enabled and operating in Full-Power mode. ...
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... PIC18F46J50 FAMILY NOTES: DS39931C-page 40 © 2009 Microchip Technology Inc. ...
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... Selecting a power-managed mode requires these decisions: • Will the CPU be clocked? • If so, which clock source will be used? © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY The IDLEN bit (OSCCON<7>) controls CPU clocking and the SCS<1:0> bits (OSCCON<1:0>) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 3-1 ...
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... SEC_RUN mode will not occur. If the Timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the oscillator has started. In such situa- tions, initial oscillator operation is far from stable and unpredictable operation may result. © 2009 Microchip Technology Inc. ...
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... Note 1024 OST OSC © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock would be providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run ...
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... SCS bits are not affected by the switch. The INTRC clock source will continue to run if either the WDT or the FSCM is enabled. block (see n-1 n Clock Transition (1) (1) T PLL 1 2 n-1 n Clock Transition OSTS Bit Set = 2 ms (approx). These intervals are not shown to scale. PLL © 2009 Microchip Technology Inc. ...
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... OST OSC PLL © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS<1:0> bits becomes ready (see Figure 3-6 will be clocked from the internal oscillator if either the Two-Speed Start-up or the FSCM are enabled (see Section 26 ...
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... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD © 2009 Microchip Technology Inc. ...
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... Idle mode, or the Sleep mode Run mode. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY T CSD PC ...
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... DSGPR0 and DSGPR1 registers. The contents of these registers are preserved while the device is in Deep Sleep, and will remain valid throughout an entire Deep Sleep entry and wake-up sequence. supply rail of DD could fall below the SRAM retention © 2009 Microchip Technology Inc. ...
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... DSGPR0 and DSGPR1 contents will remain valid. In all other Deep Sleep wake-up cases, application firmware needs to clear the RELEASE bit in order to reconfigure the I/O pins. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 3.6.3 DEEP SLEEP WAKE-UP SOURCES The device can be awakened from Deep Sleep mode by a MCLR, POR, RTCC, INT0 I/O pin interrupt, DSWDT or ULPWU event ...
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... Sleep, causing a POR Reset. During Deep Sleep, the Fault detection circuitry is always enabled and does not require any specific configuration prior to entering Deep Sleep. and DSBOR are enabled Clock and Calendar see Section 3.7 “Ultra Sleep module includes automatic © 2009 Microchip Technology Inc. ...
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... Upon waking from Deep Sleep, the I/O pins maintain their previous states. Clearing this bit will release the I/O pins and allow their respective TRIS and LAT bits to control their states. Note 1: This is the value when V DD © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY provided in U-0 U-0 — ...
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... V DD (1) R/W-xxxx U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown drops below the normal BOR threshold outside of Deep DDCORE is hard cycled to near V DD © 2009 Microchip Technology Inc. bit 0 drops below the bit 0 drops below the ...
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... The V supply POR circuit was not active, or was active, but did not detect a POR event DD Note 1: Unlike the other bits in this register, this bit can be set outside of Deep Sleep. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY U-0 U-0 U-0 — — ...
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... ULPWU peripheral can also be configured as a simple Programmable temperature sensor interrupt IL Note: For more information, refer to AN879, “Using the Microchip Ultra Low-Power Wake-up (DS00879). the DSULP Section 26.2 SERIAL RESISTOR Low-Voltage Detect (LVD) or Module” application note © 2009 Microchip Technology Inc. ...
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... OSCCONbits.IDLEN = 0; // enable deep sleep DSCONHbits.DSEN = 1; // Note: must be set just before executing Sleep(); //**************** //Enter Sleep Mode //**************** Sleep(); // for sleep, execution will resume here // for deep sleep, execution will restart at reset vector (use WDTCONbits.DS to detect) © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY DS39931C-page 55 ...
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... PIC18F46J50 FAMILY NOTES: DS39931C-page 56 © 2009 Microchip Technology Inc. ...
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... PWRT INTRC 11-Bit Ripple Counter Note 1: The Brown-out Reset is not available in PIC18F2XJ50 and PIC18F4XJ50 devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY For information on WDT Resets, see Section 26.2 “Watchdog Timer (WDT)”. For Stack Reset events, see Section 5.1.4.4 “Stack Full and Underflow Resets” ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39931C-page 58 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 POR BOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... DD DSBOR will be held in a Reset state similar to POR. All registers © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY will be set back to their POR Reset values and the con- tents of the DSGPR0 and DSGPR1 holding registers will be lost. Additionally, if any I/O pins had been ...
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... PWRT will expire. Bringing MCLR high will begin execution immediately if a clock source is available (Figure 4-4). This is useful for testing purposes synchronize more than one PIC18F device operating in parallel. T PWRT ) for PWRT , V RISE < PWRT © 2009 Microchip Technology Inc. ...
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... FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 4-5: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY T PWRT T PWRT , V RISE > 3. PWRT ): CASE 1 ...
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... These bits are used in software to determine the nature of the Reset. Table 4-2 describes the Reset states for all of the Special Function Registers. These are categorized by POR and BOR, MCLR and WDT Resets and WDT wake-ups. RCON Register ( POR STKPTR Register BOR STKFUL STKUNF © 2009 Microchip Technology Inc. ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ50 devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt N/A N/A N/A N/A ---- uuuu uuuu uuuu ---u uuuu uuuu uuuu ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ50 devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu 0uuu uuuu 0uuu uuuu uuuu uxuu ---- -uuu ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ50 devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-- uuuu uu-- uuuu ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ50 devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ...
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... Config. Words Unimplemented Read as ‘0’ Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 5.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space ...
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... Additional details on the device Configuration Words are provided in Section 26.1 “Configuration Bits”. TABLE 5-1: FLASH CONFIGURATION WORD FOR PIC18F46J50 FAMILY DEVICES Program Configuration Device Memory (Kbytes) PIC18F24J50 3FF8h to 3FFFh 16 PIC18F44J50 PIC18F25J50 7FF8h to 7FFFh 32 PIC18F45J50 PIC18F26J50 64 FFF8h to FFFFh PIC18F46J50 © 2009 Microchip Technology Inc. Word Addresses ...
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... TOSH TOSL 00h 1Ah 34h © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer (SP), STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers (SFRs) ...
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... Stack Pointer. The previous value st push pushed onto the stack then becomes the TOS value. R/W-0 R/W-0 R/W-0 SP4 SP3 SP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) R/W-0 R/W-0 SP1 SP0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... SUB1 • RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 5.1.6 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures or look-up tables in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
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... Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write Execute INST (PC) Execute INST ( Fetch INST ( Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch Internal Phase Clock Fetch INST ( Flush (NOP) Fetch SUB_1 Execute SUB_1 © 2009 Microchip Technology Inc. ...
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... MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
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... This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. © 2009 Microchip Technology Inc. ...
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... Note 1: These banks also serve as RAM buffers for USB operation. See Section 5.3.1 “USB RAM” for more information. 2: Addresses EC0h through F5Fh are not part of the Access Bank. Either the BANKED or the MOVFF instruction should be used to access these SFRs. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Data Memory Map ...
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... This is data RAM, which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upward toward the bottom of the SFR area. GPRs are not initialized by a POR and are unchanged on all other Resets. (2) From Opcode © 2009 Microchip Technology Inc. ...
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... PMADDRH and PMDOUTH share the same address and PMADDRL and PMDOUTL share the same address. PMADDRx is used in Master modes and PMDOUTx is used in Slave modes. 5: Reserved: Do not write to this location. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY ALU’s STATUS register is described later in this section. Registers related to the operation of the peripheral features are described in the chapter for that peripheral ...
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... ECBh RPOR5 RPINR4 ECAh RPOR4 RPINR3 EC9h RPOR3 RPINR2 EC8h RPOR2 RPINR1 EC7h RPOR1 — EC6h RPOR0 — EC5h — — EC4h — — EC3h — — EC2h — — EC1h — — EC0h — © 2009 Microchip Technology Inc. ...
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... The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different functions determined by the module’s operating mode. See Section 10.1.2 “Data Registers” for more information. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY • PMADDRH/L and PMDOUT2H/L: In this case, these named buffer pairs are actually the same physical registers ...
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... GO/DONE ADON 0000 0000 63, 341 ADCS1 ADCS0 0000 0000 64, 341 ULPSINK SWDTEN 1xx- 0000 64, 423 STRB STRA 00-0 0001 64, 259 PSS1BD1 PSS1BD0 0000 0000 64 2 C™ Slave mode. See Section 18.5.3.2 “Address © 2009 Microchip Technology Inc. ...
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... The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different functions determined by the module’s operating mode. See Section 10.1.2 “Data Registers” for more information. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Bit 4 Bit 3 ...
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... T4CKPS0 -000 0000 67, 217 xxxx xxxx 67, 282, 316 2 C Master mode) 0000 0000 67, 282 MSK1 MSK0 0000 0000 67, 289 UA BF 1111 1111 67, 264, 304 SSPM1 SSPM0 0000 0000 67, 264, 316 2 C™ Slave mode. See Section 18.5.3.2 “Address © 2009 Microchip Technology Inc. ...
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... The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different functions determined by the module’s operating mode. See Section 10.1.2 “Data Registers” for more information. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Bit 4 Bit 3 ...
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... IOLOCK 148 ---- ---0 ---1 1111 69, 153 ---1 1111 69, 153 ---1 1111 69, 153 ---1 1111 69, 152 ---1 1111 69, 152 69 ---1 1111 69 ---1 1111 ---1 1111 69, 151 ---1 1111 69, 151 ---1 1111 69, 150 ---1 1111 69, 150 ---1 1111 69, 150 2 C™ Slave mode. See Section 18.5.3.2 “Address © 2009 Microchip Technology Inc. ...
Page 89
... The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different functions determined by the module’s operating mode. See Section 10.1.2 “Data Registers” for more information. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Bit 4 Bit 3 Bit 2 — ...
Page 90
... The C and DC bits operate as a borrow and digit borrow bits respectively, in subtraction. R/W-x R/W-x R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) th low-order bit of the result occurred th low-order bit of the result R/W-x R/W-x (1) ( bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 91
... Literal Address as their LSB. This address specifies either a register address in one of the banks of data RAM (Section 5.3.4 “General Purpose © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Register File”), or a location in the Access Bank (Section 5.3.3 “Access Bank”) as the data source for the instruction. The Access RAM bit, ‘ ...
Page 92
... RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address. ADDWF , INDF1 , 1 FSR1H:FSR1L 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 E00h Bank 14 F00h Bank 15 FFFh Data Memory © 2009 Microchip Technology Inc. ...
Page 93
... FSR pair but without any incrementing or decrementing. Thus, writing to INDF2 or POSTDEC2 will write the same value to the FSR2H:FSR2L. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct operations ...
Page 94
... Figure 5-9. Those who desire to use byte or bit-oriented instruc- tions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 27.2.1 “Extended Instruction Syntax”. © 2009 Microchip Technology Inc. ...
Page 95
... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 000h 060h Bank 0 100h Bank 1 through ...
Page 96
... BSR remains unchanged. Direct Addressing, using the BSR to select the data memory bank, operates in the same manner as previously described. Not Accessible Bank 0 Window Bank 1 Bank 2 through Bank 14 Bank 15 SFRs Data Memory 00h Bank 1 “Window” 5Fh 60h SFRs FFh Access Bank © 2009 Microchip Technology Inc. ...
Page 97
... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 98
... Reset write operation was Reading attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Table Latch (8-bit) TABLAT © 2009 Microchip Technology Inc. ...
Page 99
... Initiates a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software Write cycle is complete bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-0 R/W-x R/W-0 FREE ...
Page 100
... Figure 6-3 illustrates the relevant boundaries of TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TABLE READ: TBLPTR<21:0> TBLPTRL 0 © 2009 Microchip Technology Inc. ...
Page 101
... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVWF WORD_ODD © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 102
... The CPU will stall for the duration of the erase for T (see parameter D133B Re-enable interrupts. ; load TBLPTR with the base ; address of the memory block ; enable write to memory ; enable Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts © 2009 Microchip Technology Inc. ...
Page 103
... Write the 64 bytes into the holding registers with auto-increment. 7. Set the WREN bit (EECON1<2>) to enable byte writes. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device ...
Page 104
... TBLWT holding register. ; loop until buffers are full ; enable write to memory ; disable interrupts ; write 55h ; write 0AAh ; start program (CPU stall) ; re-enable interrupts ; disable write to memory ; done with one write cycle ; if not done replacing the erase block © 2009 Microchip Technology Inc. ...
Page 105
... MOVWF EECON2 BSF EECON1, WR BSF INTCON, GIE BCF EECON1, WPROG BCF EECON1, WREN © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 3. Set the WREN bit (EECON1<2>) to enable writes and the WPROG bit (EECON1<5>) to select Word Write mode. 4. Disable interrupts. 5. Write 55h to EECON2. ...
Page 106
... See Section 26.6 “Program Verification and Code Protection” for details on code protection of Flash program memory. Bit 4 Bit 3 Bit 2 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) INT0IE RBIE TMR0IF FREE WRERR WREN Reset Bit 1 Bit 0 Values on Page INT0IF RBIF — 65 © 2009 Microchip Technology Inc. ...
Page 107
... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY EXAMPLE 7- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
Page 108
... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2009 Microchip Technology Inc. ...
Page 109
... Individual interrupts can be disabled through their corresponding enable bits. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
Page 110
... IPEN PEIE/GIEL IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP © 2009 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...
Page 111
... None of the RB<7:4> pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB and waiting 1 T condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Note: Interrupt flag bits are set when an interrupt ...
Page 112
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39931C-page 112 R/W-1 R/W-1 R/W-1 INTEDG2 INTEDG3 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 113
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-0 ...
Page 114
... R-0 R/W-0 R/W-0 TX1IF SSP1IF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 115
... A TMR1/TMR3 register capture occurred (must be cleared in software TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-0 R/W-0 R/W-0 USBIF BCL1IF HLVDIF U = Unimplemented bit, read as ‘ ...
Page 116
... RTCCIF: RTCC Interrupt Flag bit 1 = RTCC interrupt occurred (must be cleared in software RTCC interrupt occurred DS39931C-page 116 R/W-0 R/W-0 R/W-0 TX2IF TMR4IF CTMUIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 TMR3GIF RTCCIF bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 117
... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: These bits are unimplemented on 28-pin devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-0 R/W-0 R/W-0 TX1IE SSP1IE CCP1IE U = Unimplemented bit, read as ‘ ...
Page 118
... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: ECCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS39931C-page 118 R/W-0 R/W-0 R/W-0 USBIE BCL1IE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 TMR3IE CCP2IE bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 119
... Enabled 0 = Disabled bit 1 TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 RTCCIE: RTCC Interrupt Enable bit 1 = Enabled 0 = Disabled © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-0 R/W-0 R/W-0 TX2IE TMR4IE CTMUIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 120
... TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: These bits are unimplemented on 28-pin devices. DS39931C-page 120 R/W-1 R/W-1 R/W-1 TX1IP SSP1IP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 121
... Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-1 R/W-1 R/W-1 USBIP BCL1IP HLVDIP U = Unimplemented bit, read as ‘0’ ...
Page 122
... Low priority bit 0 RTCCIP: RTCC Interrupt Priority bit 1 = High priority 0 = Low priority DS39931C-page 122 R/W-1 R/W-1 R/W-1 TX2IP TMR4IP CTMUIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 TMR3GIP RTCCIP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 123
... For details on bit operation, see Register 4-1. bit 1 POR: Power-on Reset Status bit For details on bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details on bit operation, see Register 4-1. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘ ...
Page 124
... Example 8-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS © 2009 Microchip Technology Inc. ...
Page 125
... EN RD PORT Note 1: I/O pins have diode protection © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 9.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 9 ...
Page 126
... TTL buffers with the PMPTTL bit in the PADCFG1 reg- ister (Register 9-4). Setting this bit configures all data and control input pins for the PMP to use TTL buffers. By default, these PMP inputs use the port’s ST buffers. © 2009 Microchip Technology Inc. 5V ...
Page 127
... U2OD: USART2 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled bit 0 U1OD: USART1 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ...
Page 128
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 R/W-0 (1) — — RTSECSEL1 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 SPI2OD SPI1OD bit Bit is unknown R/W-0 R/W-0 (1) RTSECSEL0 PMPTTL bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 129
... The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY EXAMPLE 9-2: INITIALIZING PORTA ...
Page 130
... LATA<3> data output; not affected by analog input. I TTL PORTA<3> data input; disabled when analog input enabled. I ANA A/D input channel 3 and Comparator C1+ input. Default input configuration on POR. I ANA A/D and comparator voltage reference high input. I ANA Comparator 1 input B output enabled. REF © 2009 Microchip Technology Inc. ...
Page 131
... COE CVRCON CVREN CVROE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: These bits are only available in 44-pin devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY I/O I/O Type O DIG LATA<5> data output; not affected by analog input. ...
Page 132
... PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. The RB5 pin is multiplexed with the Timer0 module clock input and one of the comparator outputs to become the RB5/KBI1/SDI1/SDA1/RP8 pin. © 2009 Microchip Technology Inc. ...
Page 133
... Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default when PBADEN is set and digital inputs when PBADEN is cleared. 2: All other pin functions are disabled when ICSP™ or ICD are enabled. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY I/O I/O ...
Page 134
... PORTB<7> data input; weak pull-up when RBPU bit is cleared. I TTL Interrupt-on-change pin. O DIG Serial execution data output for ICSP and ICD operation Serial execution data input for ICSP and ICD operation Remappable peripheral pin 10 input Remappable peripheral pin 10 output. Description (1) (2) (2) © 2009 Microchip Technology Inc. ...
Page 135
... INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INTCON3 INT2IP INT1IP ADCON0 PCFG7 PCFG6 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 LATB5 ...
Page 136
... ANCON1,PCFG11 like all DD INITIALIZING PORTC ; Initialize PORTC by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RC<5:0> as inputs ; RC<7:6> as outputs ; ANCON register is not in Access Bank ;Configure RC2/AN11 as digital input © 2009 Microchip Technology Inc. ...
Page 137
... C/SMBus input buffer Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: Enhanced PWM output is available only on PIC18F4XJ50 devices. 2: This bit is only available on 44-pin devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY (1) I/O I/O Type ...
Page 138
... Remappable peripheral pin 18 input. O DIG Remappable peripheral pin 18 output. Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 — RC2 LATC5 LATC4 — LATC2 TRISC5 TRISC4 — TRISC2 Description Reset Bit 1 Bit 0 Values on page: RC1 RC0 86 LATC1 LATC0 86 TRISC1 TRISC0 86 © 2009 Microchip Technology Inc. ...
Page 139
... Legend: DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer; I input buffer Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY EXAMPLE 9-5: CLRF ...
Page 140
... Remappable peripheral pin 24 input. O DIG Remappable peripheral pin 24 output. Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 LATD5 LATD4 LATD3 LATD2 TRISD4 TRISD3 TRISD2 Description 2 2 C/SMB = I C/SMBus Reset Bit 1 Bit 0 Values on page RD1 RD0 86 LATD1 LATD0 86 TRISD1 TRISD0 86 © 2009 Microchip Technology Inc. ...
Page 141
... Note POR, RE<2:0> are configured as analog inputs. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register read and write the latched output value for PORTE ...
Page 142
... USB voltage input pin. Bit 5 Bit 4 Bit 3 Bit 2 — — — RE2 — — — LATE2 — — — TRISE2 (2) PCFG4 PCFG3 PCFG2 Description Reset Bit 1 Bit 0 Values on page RE1 RE0 86 LATE1 LATE0 86 TRISE1 TRISE0 86 PCFG1 PCFG0 88 © 2009 Microchip Technology Inc. ...
Page 143
... PPS feature include the designation “RPn” in their full pin designation, where “RP” designates a remappable peripheral and “n” is the remappable pin number. See Table 1-2 for pinout options in each package offering. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 9.7.2 AVAILABLE PERIPHERALS The peripherals managed by the PPS are all digital only peripherals ...
Page 144
... RPINR7 CCP2 RPINR8 T1G RPINR12 T3G RPINR13 RX2/DT2 RPINR16 CK2 RPINR17 SDI2 RPINR21 SCK2IN RPINR22 SS2IN RPINR23 FLT0 RPINR24 © 2009 Microchip Technology Inc. Configuration Bits INTR1R<4:0> INTR2R<4:0> INTR3R<4:0> T0CKR<4:0> T3CKR<4:0> IC1R<4:0> IC2R<4:0> T1GR<4:0> T3GR<4:0> RX2DT2R<4:0> CK2R<4:0> SDI2R<4:0> SCK2R<4:0> SS2R<4:0> OCFAR<4:0> ...
Page 145
... Value assigned to the RP<4:0> pins corresponds to the peripheral output function number. 2: The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Because of the mapping technique, the list of peripherals for output mapping also includes a null value of ‘ ...
Page 146
... The unlock sequence is timing critical. Therefore recommended that the unlock sequence be executed as an assembly language routine with interrupts temporarily disabled. If the bulk of the application is written another high-level language, the unlock sequence should be performed by writing in-line assembly. © 2009 Microchip Technology Inc. ...
Page 147
... Example 9-7 provides a configuration for bidirectional communication with flow control using EUSART2. The following input and output functions are used: • Input Function RX2 • Output Function TX2 © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY EXAMPLE 9-7: CONFIGURING EUSART2 INPUT AND OUTPUT ...
Page 148
... Input and output register values can only be changed if PPS<IOLOCK> See Example 9-7 for a specific command sequence. U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. (1) U-0 R/W-0 — IOLOCK bit Bit is unknown ...
Page 149
... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 INTR3R<4:0>: Assign External Interrupt 3 (INT3) to the Corresponding RPn Pin bits © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-1 R/W-1 R/W-1 INTR1R4 INTR1R3 INTR1R2 U = Unimplemented bit, read as ‘ ...
Page 150
... R/W-1 R/W-1 R/W-1 IC1R4 IC1R3 IC1R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 T0CKR1 T0CKR0 bit Bit is unknown R/W-1 R/W-1 T3CKR1 T3CKR0 bit Bit is unknown R/W-1 R/W-1 IC1R1 IC1R0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 151
... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 T3GR<4:0>: Timer3 Gate Input (T3G) to the Corresponding RPn Pin bits © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-1 R/W-1 R/W-1 IC2R4 IC2R3 IC2R2 U = Unimplemented bit, read as ‘ ...
Page 152
... R/W-1 R/W-1 R/W-1 SDI2R4 SDI2R3 SDI2R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 RX2DT2R1 RX2DT2R0 bit Bit is unknown R/W-1 R/W-1 CK2R1 CK2R0 bit Bit is unknown R/W-1 R/W-1 SDI2R1 SDI2R0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 153
... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 OCFAR<4:0>: Assign PWM Fault Input (FLT0) to the Corresponding RPn Pin bits © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-1 R/W-1 R/W-1 SCK2R4 SCK2R3 SCK2R2 U = Unimplemented bit, read as ‘ ...
Page 154
... R/W-0 R/W-0 R/W-0 RP2R4 RP2R3 RP2R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RP0R1 RP0R0 bit Bit is unknown R/W-0 R/W-0 RP1R1 RP1R0 bit Bit is unknown R/W-0 R/W-0 RP2R1 RP2R0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 155
... Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP5R<4:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits (see Table 9-14 for peripheral function numbers) © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-0 R/W-0 R/W-0 RP3R4 RP3R3 RP3R2 U = Unimplemented bit, read as ‘ ...
Page 156
... R/W-0 R/W-0 R/W-0 RP8R4 RP8R3 RP8R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RP6R1 RP6R0 bit Bit is unknown R/W-0 R/W-0 RP7R1 RP7R0 bit Bit is unknown R/W-0 R/W-0 RP8R1 RP8R0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 157
... Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 9-14 for peripheral function numbers) © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-0 R/W-0 R/W-0 RP9R4 RP9R3 RP9R2 U = Unimplemented bit, read as ‘ ...
Page 158
... R/W-0 R/W-0 R/W-0 RP17R4 RP17R3 RP17R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RP12R1 RP12R0 bit Bit is unknown R/W-0 R/W-0 RP13R1 RP13R0 bit Bit is unknown R/W-0 R/W-0 RP17R1 RP17R0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 159
... Unimplemented: Read as ‘0’ bit 4-0 RP20R<4:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits (see Table 9-14 for peripheral function numbers) Note 1: RP20 pins are not available on 28-pin devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-0 R/W-0 R/W-0 RP18R4 ...
Page 160
... R/W-0 R/W-0 R/W-0 RP23R4 RP23R3 RP23R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 RP21R1 RP21R0 bit Bit is unknown (1) R/W-0 R/W-0 RP22R1 RP22R0 bit Bit is unknown (1) R/W-0 R/W-0 RP23R1 RP23R0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 161
... Unimplemented: Read as ‘0’ bit 4-0 RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table 9-14 for peripheral function numbers) Note 1: RP24 pins are not available on 28-pin devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-0 R/W-0 R/W-0 RP24R4 ...
Page 162
... PIC18F46J50 FAMILY NOTES: DS39931C-page 162 © 2009 Microchip Technology Inc. ...
Page 163
... PMP Parallel Slave Port (PSP). FIGURE 10-1: PMP MODULE OVERVIEW PIC18 Parallel Master Port © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Key features of the PMP module are: • bits of addressing when using data/address multiplexing • Programmable Address Lines • ...
Page 164
... R/W-0 R/W-0 R/W-0 ADRMUX1 ADRMUX0 PTBEEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (Register 10-1 and registers (Register 10-3 and (Register 10-5 and (1) R/W-0 R/W-0 PTWREN PTRDEN bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 165
... For Master Mode 1 (PMMODEH<1:0> Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) Note 1: This register is only available in 44-pin devices. 2: These bits have no effect when their corresponding pins are used as address lines. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY (2) (2) U-0 R/W-0 — ...
Page 166
... Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>) Note 1: This register is only available in 44-pin devices. DS39931C-page 166 R/W-0 R/W-0 R/W-0 INCM1 INCM0 MODE16 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 MODE1 MODE0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 167
... Wait Wait Note 1: This register is only available in 44-pin devices. 2: WAITBx and WAITEx bits are ignored whenever WAITM<3:0> = 0000. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R/W-0 R/W-0 WAITM2 WAITM1 WAITM0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ; multiplexed address phase ...
Page 168
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 PTEN4 PTEN3 PTEN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 PTEN9 PTEN8 bit Bit is unknown (1) R/W-0 R/W-0 PTEN1 PTEN0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 169
... OB3E:OB0E: Output Buffer x Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit Output buffer contains data that has not been transmitted Note 1: This register is only available in 44-pin devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY U-0 R-0 R-0 — ...
Page 170
... This option allows users to select either the normal Schmitt Trigger input buffer on digital I/O pins shared with the PMP, or use TTL level compatible buffers instead. Buffer configuration is controlled by the PMPTTL bit in the PADCFG1 register. © 2009 Microchip Technology Inc. ...
Page 171
... Value at POR ‘1’ = Bit is set bit 7-0 Parallel Master Port Address: Low Byte<7:0> bits Note 1: In Enhanced Slave mode, PMADDRL functions as PMDOUT1L, one of the Output Data Buffer registers. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY (1) R/W-0 R/W-0 R/W-0 Parallel Master Port Address High Byte<13:8> ...
Page 172
... Figure 10-2 displays the connection of the PSP. When chip select is active and a write strobe occurs and (PMCS = 1 and PMWR = 1), the data from PMD<7:0> is captured into the PMDIN1L register. PIC18 Slave PMD<7:0> PMCS PMRD PMWR Address Bus Data Bus Control Lines © 2009 Microchip Technology Inc. ...
Page 173
... PMCS1 PMWR PMRD PMD<7:0> IBF OBE PMPIF © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 10.2.3 READ FROM SLAVE PORT When chip select is active and a read strobe occurs (PMCS = 1 and PMRD = 1), the data from the PMDOUT1L register (PMDOUT1L<7:0>) is presented onto PMD<7:0>. Figure 10-4 provides the timing for the control signals in Read mode ...
Page 174
... IBxF flags. If these flags are not cleared, then there is a risk of hitting an overflow condition. PIC18 Slave Write Read PMD<7:0> Address Address Pointer Pointer PMDOUT1L (0) PMCS PMDOUT1H (1) PMDOUT2L (2) PMRD PMDOUT2H (3) PMWR © 2009 Microchip Technology Inc. PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3) ...
Page 175
... ADDR<1:0>. Table 10-1 provides the corresponding FIGURE 10-7: PARALLEL SLAVE PORT READ WAVEFORMS PMCS PMWR PMRD PMD<7:0> PMA<1:0> OBE PMPIF © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY TABLE 10-1: SLAVE MODE BUFFER ADDRESSING Output PMA<1:0> Register (Buffer) PMDOUT1L (0) 00 ...
Page 176
... When an input buffer is written, the corresponding IBxF bit is set. The IBF flag bit is set when all the buffers are written. If any buffer is already written (IBxF = 1), the next write strobe to that buffer will generate an OBUF event and the byte will be discarded © 2009 Microchip Technology Inc ...
Page 177
... PMAL and PMCSx) can be individually configured as either positive or negative polarity. Configuration is controlled by separate bits in the PMCONL register. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Note that the polarity of control signals that share the same output pin (for example, PMWR and PMENB) are controlled by the same bit ...
Page 178
... Address Bus PMRD Data Bus PMWR Control Lines PMD<7:0> PMA<7:0> PMCS PMALL Address Bus Multiplexed PMRD Data and Address Bus PMWR Control Lines PMD<7:0> PMA<13:8> PMCS PMALL PMALH Multiplexed Data and PMRD Address Bus PMWR Control Lines © 2009 Microchip Technology Inc. ...
Page 179
... The first read data byte is placed into the PMDIN1L register, and the second read data is placed into the PMDIN1H. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Note that the read data obtained from the PMDIN1L register is actually the read value from the previous read operation ...
Page 180
... BUSY FIGURE 10-14: READ TIMING, 8-BIT DATA, WAIT STATES ENABLED, PARTIALLY MULTIPLEXED ADDRESS PMCS1 Address<7:0> PMD<7:0> PMRD PMWR PMALL PMPIF BUSY WAITB<1:0> DS39931C-page 180 Data Data WAITE<1:0> WAITM<3:0> = 0010 © 2009 Microchip Technology Inc. ...
Page 181
... PMCS1 PMD<7:0> Address<7:0> PMWR PMRD PMALL PMPIF BUSY WAITB<1:0> FIGURE 10-17: READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE PMCS1 PMD<7:0> Address<7:0> PMRD/PMWR PMENB PMALL PMPIF BUSY © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Data Data WAITE<1:0> WAITM<3:0> = 0010 Data ...
Page 182
... READ TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS1 Address<7:0> PMD<7:0> PMWR PMRD PMALL PMALH PMPIF BUSY FIGURE 10-20: WRITE TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS1 PMD<7:0> Address<7:0> PMWR PMRD PMALL PMALH PMPIF BUSY DS39931C-page 182 Data Address<13:8> Data Address<13:8> Data © 2009 Microchip Technology Inc. ...
Page 183
... WRITE TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS PMCS1 PMD<7:0> PMA<7:0> PMWR PMRD PMBE PMPIF BUSY FIGURE 10-23: READ TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS PMCS1 PMD<7:0> Address<7:0> PMWR PMRD PMBE PMALL PMPIF BUSY © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY LSB MSB LSB MSB LSB MSB ...
Page 184
... PMBE PMALH PMALL PMPIF BUSY FIGURE 10-26: WRITE TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS1 Address<7:0> PMD<7:0> PMWR PMRD PMBE PMALH PMALL PMPIF BUSY DS39931C-page 184 LSB MSB Address<13:8> LSB Address<13:8> LSB MSB MSB © 2009 Microchip Technology Inc. ...
Page 185
... EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION PIC18F PMD<7:0> PMALL PMCS PMRD PMWR © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 10.4.1 MULTIPLEXED MEMORY OR PERIPHERAL Figure 10-27 demonstrates the hookup of a memory or another addressable peripheral in Full Multiplex mode. Consequently, this mode achieves the best pin saving from the microcontroller perspective ...
Page 186
... PM<7:0> PMA0 PMRD/PMWR PMCS DS39931C-page 186 Parallel EEPROM A<n:0> D<7:0> Parallel EEPROM A<n:1> D<7:0> LCD Controller D<7:0> RS R/W E Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines © 2009 Microchip Technology Inc. ...
Page 187
... The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. 2: These bits and/or registers are only available in 44-pin devices. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Bit 5 Bit 4 Bit 3 ...
Page 188
... PIC18F46J50 FAMILY NOTES: DS39931C-page 188 © 2009 Microchip Technology Inc. ...
Page 189
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. Figure 11-1 provides a simplified block diagram of the Timer0 module in 8-bit mode ...
Page 190
... Sync with Internal TMR0L Clocks Delay There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
Page 191
... INTCON GIE/GIEH PEIE/GIEL TMR0IE T0CON TMR0ON T08BIT Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
Page 192
... PIC18F46J50 FAMILY NOTES: DS39931C-page 192 © 2009 Microchip Technology Inc. ...
Page 193
... The circuit is enabled by the logical OR of these two bits. When disabled, the inverter and feedback resistor are disabled to eliminate power drain. The TMR1ON and TMR3ON bits do not have to be enabled to power up the crystal driver. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY Figure 12-1 displays a simplified block diagram of the Timer1 module ...
Page 194
... TMR2 to match PR2 output Note 1: Programming the T1GCON prior to T1CON is recommended. DS39931C-page 194 (T1GCON), R/W-0 R/W-0 R-x T1GVAL T1GSPM T1GGO/T1DONE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 T1GSS1 T1GSS0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 195
... ECCP1 and ECCP2 both use Timer3 (capture/compare) and Timer4 (PWM ECCP1 uses Timer1 (compare/capture) and Timer2 (PWM); ECCP2 uses Timer3 (capture/compare) and Timer4 (PWM ECCP1 and ECCP2 both use Timer1 (capture/compare) and Timer2 (PWM) © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY R-0 U-0 ...
Page 196
... Timer1 is disabled (TMR1ON = 0) when T1CKI is high, then Timer1 is enabled (TMR1ON = 1) when T1CKI is low. T1OSCEN Clock Source (F x Instruction Clock (F x External Clock on T1CKI Pin 0 Oscillator Circuit on T1OSI/T1OSO Pin 1 system clock or they can run Clock Source ) OSC /4) OSC © 2009 Microchip Technology Inc. ...
Page 197
... TMR1H T1OSO/T1CKI OUT T1OSC T1OSI EN T1OSCEN T1CKI Note 1: ST Buffer is high-speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY T1GSPM T1G_IN 0 Single Pulse Acq. Control T1GGO/T1DONE CK R TMR1ON ...
Page 198
... C1 and C2 for a given crystal. The optimum value depends in part on the amount of parasitic capacitance in the circuit, which is often unknown. Therefore, after values have been selected highly recommended that thorough testing and validation of the oscillator be performed. © 2009 Microchip Technology Inc external ...
Page 199
... OSC2 pin), a grounded guard ring around the oscillator circuit, as displayed in Figure 12-3, may be helpful when used on a single-sided PCB or in addition to a ground plane. © 2009 Microchip Technology Inc. PIC18F46J50 FAMILY FIGURE 12-3: Note: Not drawn to scale. In the Low Drive Level mode, LPT1OSC = critical that the RC2 I/O pin signals be kept away from the oscillator circuit ...
Page 200
... Timer1 will hold the current count. See Figure 12-4 for timing details. TABLE 12-3: TIMER1 GATE ENABLE SELECTIONS T1CLK T1GPOL T1G ↑ ↑ ↑ ↑ © 2009 Microchip Technology Inc. Timer1 Operation Counts Holds Count Holds Count Counts ...