PIC24FJ64GA002-I/SP Microchip Technology, PIC24FJ64GA002-I/SP Datasheet - Page 30

• Manufacturer Part Number: PIC24FJ64GA002-I/SP
• Description: IC PIC MCU FLASH 21KX24 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA002-I/SP

• Core Size: 16-Bit
• Program Memory Size: 64KB (22K x 24)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC24
• No. Of I/o's: 21
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164337 - MODULE SOCKET FOR PM3 40DIPDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC24FJXXXGA0XX
4.5.2
After code memory is programmed, the contents of
memory can be verified to ensure that programming
was successful. Verification requires code memory to
be read back and compared against the copy held in
the programmer’s buffer.
The READP command can be used to read back all of
the programmed code memory.
Alternatively, you can have the programmer perform
the verification after the entire device is programmed
using a checksum computation.
TABLE 4-2:
DS39768D-page 30
I2C1SEL
DEBUG
FCKSM1:FCKSM0
FNOSC2:FNOSC0
FWDTEN
GCP
GWRP
ICS
Note 1:
Bit Field
2:
(1)
Available on 28 and 44-pin packages only.
Available only on 28 and 44-pin devices with a silicon revision of 3042h or higher.
PROGRAMMING VERIFICATION
PIC24FJXXXGA0XX FAMILY CONFIGURATION BITS DESCRIPTION
CW2<10:8>
CW2<7:6>
CW1<13>
CW1<12>
CW1<11>
Register
CW2<2>
CW1<7>
CW1<8>
I2C1 Pin Mapping bit
1 = Default location for SCL1/SDA1 pins
0 = Alternate location for SCL1/SDA1 pins
Background Debug Enable bit
1 = Device will reset in User mode
0 = Device will reset in Debug mode
Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
Initial Oscillator Source Selection bits
111 = Internal Fast RC (FRCDIV) oscillator with postscaler
110 = Reserved
101 = Low-Power RC (LPRC) oscillator
100 = Secondary (SOSC) oscillator
011 = Primary (XTPLL, HSPLL, ECPLL) oscillator with PLL
010 = Primary (XT, HS, EC) oscillator
001 = Internal Fast RC (FRCPLL) oscillator with postscaler and PLL
000 = Fast RC (FRC) oscillator
Watchdog Timer Enable bit
1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled;
0 = Watchdog Timer enabled/disabled by user software (LPRC can be
General Segment Code-Protect bit
1 = User program memory is not code-protected
0 = User program memory is code-protected
General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
ICD Communication Channel Select bit
1 = Communicate on PGC2/EMUC2 and PGD2/EMUD2
0 = Communicate on PGC1/EMUC1 and PGD1/EMUD1
clearing the SWDTEN bit in the RCON register will have no effect)
disabled by clearing the SWDTEN bit in the RCON register)
4.6
4.6.1
The PIC24FJXXXGA0XX family has Configuration bits
stored in the last two locations of implemented program
memory (see Table 2-2 for locations). These bits can
be set or cleared to select various device configura-
tions. There are three types of Configuration bits:
system operation bits, code-protect bits and unit ID bits.
The system operation bits determine the power-on
settings for system level components, such as
oscillator and Watchdog Timer. The code-protect bits
prevent program memory from being read and written.
The register descriptions for the CW1 and CW2
Configuration registers are shown in Table 4-2.
Configuration Bits Programming
Description
OVERVIEW
© 2008 Microchip Technology Inc.