PIC24FJ48GA002-E/SP Microchip Technology, PIC24FJ48GA002-E/SP Datasheet - Page 10

• Manufacturer Part Number: PIC24FJ48GA002-E/SP
• Description: IC PIC MCU FLASH 48K 28-SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ48GA002-E/SP

• Program Memory Type: FLASH
• Program Memory Size: 48KB (16K x 24)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DV164033, MA240013, DM300027, AC164127, DM240002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164337 - MODULE SOCKET FOR PM3 40DIPDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ64GA004 FAMILY
22. Module: I/O Ports
23. Module: JTAG
24. Module: RTCC
DS80470E-page 10
During Power-on Reset (POR), the device may
drive the OSCO/RA3 pin as a clock out output for
approximately 20 S. During this time, the pin will
be driven high and low rather than being set to
high-impedance. This may cause issues on
designs that use the pin as a general purpose I/O.
Designs should be reviewed to ensure that their
intended operation will not be disrupted if the pin is
driven during POR.
Work around
None.
Affected Silicon Revisions
When entering the SHIFT_DR state while in
ICSP™ Communications mode, an extra clock
edge may be generated, causing JTAG and ICSP
communications to lose synchronization. This
prevents device programming using ICSP over
JTAG. JTAG boundary scan is not affected and
operates as expected.
Work around
None.
Affected Silicon Revisions
When performing writes to the ALCFGRPT regis-
ter, some bits may become corrupted. The error
occurs because of desynchronization between the
CPU clock domain and the RTCC clock domain.
The error causes data, from the instruction
following the ALCFGRPT instruction, to overwrite
the data in ALCFGRPT.
A3/
A3/
A4
A4
X
X
B4
B4
B5
B5
B8
B8
25. Module: I
Work around
Always follow writes to the ALCFGRPT register
with an additional write of the same data to a
dummy location. These writes can be performed to
RAM locations, W registers or unimplemented
SFR space.
The optimal way to perform the work around:
1. Read ALCFGRPT into a RAM location.
2. Modify the ALCFGRPT data, as required, in
3. Move the RAM value into ALCFGRPT, and a
Affected Silicon Revisions
When the I
after the ACKSTAT bit is set when receiving a
NACK from the master, it may be cleared by the
reception of a Start or Stop bit.
Due to this issue, the state of ACKSTAT after a
transmission finishes will vary depending on
device revision. On revisions with this issue,
ACKSTAT will be clear at the end of the transmis-
sion, and will remain clear until the next NACK is
received from the Master. On revisions without the
issue, ACKSTAT will be set at the end of a trans-
mission and will remain set until receiving an ACK
from the Master.
Work around
Store the value of the ACKSTAT bit immediately
after receiving a NACK from the master.
Affected Silicon Revisions
A3/
A3/
A4
A4
X
X
RAM.
dummy location, in back-to-back instructions.
B4
B4
2
2
C module is operating in Slave mode,
C
B5
B5
 2010 Microchip Technology Inc.
B8
B8