PIC16C63A-04/SP Microchip Technology, PIC16C63A-04/SP Datasheet - Page 70

• Manufacturer Part Number: PIC16C63A-04/SP
• Description: IC MCU OTP 4KX14 PWM 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C63A-04/SP

• Program Memory Type: OTP
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: I2C/SPI/USART
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVMCPA - KIT DVR BOARD EVAL SYSTEM MXDEV1
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16C63A/65B/73B/74B
11.2.2
The receiver block diagram is shown in Figure 11-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter oper-
ates at the bit rate or at F
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG register (if
it is empty). If the transfer is complete, USART Receive
Flag bit RCIF (PIR1<5>) is set. This interrupt can be
enabled/disabled by setting/clearing the USART
Receive Enable bit RCIE (PIE1<5>).
Flag bit RCIF is a read only bit, which is cleared by the
hardware. It is cleared when the RCREG register has
been read and is empty. The RCREG is a double buff-
FIGURE 11-4:
DS30605C-page 70
F
OSC
USART ASYNCHRONOUS
RECEIVER
RC7/RX/DT
Baud Rate Generator
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
OSC
SPBRG
Pin Buffer
and Control
SPEN
.
Data
Recovery
Interrupt
CREN
or
64
16
ered register, i.e., it is a two-deep FIFO. It is possible
for two bytes of data to be received and transferred to
the RCREG FIFO and a third byte to begin shifting to
the RSR register. On the detection of the STOP bit of
the third byte, if the RCREG register is still full, then
overrun error bit OERR (RCSTA<1>) will be set. The
word in the RSR will be lost. The RCREG register can
be read twice to retrieve the two bytes in the FIFO.
Overrun bit OERR has to be cleared in software. This
is done by resetting the receive logic (CREN is cleared
and then set). If bit OERR is set, transfers from the
RSR register to the RCREG register are inhibited, and
no further data will be received; therefore, it is essential
to clear error bit OERR if it is set. Framing error bit
FERR (RCSTA<2>) is set if a STOP bit is detected as
clear. Bit FERR and the 9th receive bit are buffered the
same way as the receive data. Reading the RCREG
will load bits RX9D and FERR with new values, there-
fore, it is essential for the user to read the RCSTA reg-
ister before reading the RCREG register, in order not to
lose the old FERR and RX9D information.
RCIF
RCIE
RX9
STOP
MSb
RX9D
(8)
OERR
7
RSR Register
RCREG Register
8
Data Bus
2000 Microchip Technology Inc.
1
FERR
0
START
LSb
FIFO