DSPIC33FJ32MC202-I/SP Microchip Technology, DSPIC33FJ32MC202-I/SP Datasheet - Page 170

• Manufacturer Part Number: DSPIC33FJ32MC202-I/SP
• Description: IC DSPIC MCU/DSP 32K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ32MC202-I/SP

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 32KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28SPDIP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit|6-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
REGISTER 15-10: P
DS70283H-page 170
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13-8
bit 7-6
bit 5-0
Note 1:
U-0
U-0
—
—
PWM2 supports only 1 PWM I/O pin pair.
Unimplemented: Read as ‘0’
POVDxH<3:1>:POVDxL<3:1>: PWM Output Override bits
1 = Output on PWMx I/O pin is controlled by the PWM generator
0 = Output on PWMx I/O pin is controlled by the value in the corresponding POUTxH:POUTxL bit
Unimplemented: Read as ‘0’
POUTxH<3:1>:POUTxL<3:1>: PWM Manual Output bits
1 = PWMx I/O pin is driven active when the corresponding POVDxH:POVDxL bit is cleared
0 = PWMx I/O pin is driven inactive when the corresponding POVDxH:POVDxL bit is cleared
U-0
U-0
—
—
x
OVDCON: OVERRIDE CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
POVD3H
POUT3H
R/W-1
R/W-0
POVD3L
POUT3L
R/W-1
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
POVD2H
POUT2H
R/W-1
R/W-0
POVD2L
POUT2L
R/W-1
R/W-0
(1)
© 2011 Microchip Technology Inc.
x = Bit is unknown
POVD1H
POUT1H
R/W-1
R/W-0
POVD1L
POUT1L
R/W-1
R/W-0
bit 8
bit 0