PIC16F84A-04/SO Microchip Technology, PIC16F84A-04/SO Datasheet - Page 305

• Manufacturer Part Number: PIC16F84A-04/SO
• Description: IC MCU FLASH 1KX14 EE 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F84A-04/SO

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Eeprom Size: 64 x 8
• Ram Size: 68 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 68 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILI3-DB16F84A - BOARD DAUGHTER ICEPIC3309-1075 - ADAPTER 18-SOIC TO 18-SOIC309-1011 - ADAPTER 18-SOIC TO 18-DIP309-1010 - ADAPTER 18-SOIC TO 18-DIPAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.4.6
17.4.7
1997 Microchip Technology Inc.
Multi-Master Mode
I
2
C Master Mode Support
In multi-master mode, the interrupt generation on the detection of the START and STOP condi-
tions allows the determination of when the bus is free. The STOP (P) and START (S) bits are
cleared from a reset or when the SSP module is disabled. Control of the I
when the P bit (SSPSTAT<4>) is set, or the bus is idle with both the S and P bits clear. When the
bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition
occurs.
In multi-master operation, the SDA line must be monitored, for arbitration, to see if the signal level
is the expected output level. This check is performed in hardware, with the result placed in the
BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
Master Mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by
setting the SSPEN bit. Once master mode is enabled, the user has six options.
1.
2.
3.
4.
5.
6.
Note:
Assert a start condition on SDA and SCL.
Assert a Repeated Start condition on SDA and SCL.
Write to the SSPBUF register initiating transmission of data/address.
Generate a stop Condition on SDA and SCL.
Configure the I
Generate an acknowledge condition at the end of a received byte of data.
The SSP Module when configured in I
events. For instance: The user is not allowed to initiate a start condition, and imme-
diately write the SSPBUF register to imitate transmission before the START condi-
tion is complete. In this case the SSPBUF will not be written to, and the WCOL bit
will be set, indicating that a write to the SSPBUF did not occur.
2
C port to receive data.
Preliminary
Section 17. MSSP
2
C Master Mode does not allow queueing of
2
DS31017A-page 17-29
C bus may be taken
17