PIC16F84A-20/SO Microchip Technology, PIC16F84A-20/SO Datasheet - Page 34

• Manufacturer Part Number: PIC16F84A-20/SO
• Description: IC MCU FLASH 1KX14 EE 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F84A-20/SO

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 68 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC16F
• No. Of I/o's: 13
• Eeprom Memory Size: 64Byte
• Ram Memory Size: 68Byte
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 68 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILI3-DB16F84A - BOARD DAUGHTER ICEPIC3309-1075 - ADAPTER 18-SOIC TO 18-SOIC309-1011 - ADAPTER 18-SOIC TO 18-DIP309-1010 - ADAPTER 18-SOIC TO 18-DIPAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

PIC16F84A
6.11
A device may be powered down (SLEEP) and later
powered up (wake-up from SLEEP).
6.11.1
The Power-down mode is entered by executing the
SLEEP instruction.
If enabled, the Watchdog Timer is cleared (but keeps
running), the PD bit (STATUS<3>) is cleared, the TO bit
(STATUS<4>) is set, and the oscillator driver is turned
off. The I/O ports maintain the status they had before
the SLEEP instruction was executed (driving high, low,
or hi-impedance).
For the lowest current consumption in SLEEP mode,
place all I/O pins at either V
circuitry drawing current from the I/O pins, and disable
external clocks. I/O pins that are hi-impedance inputs
should be pulled high or low externally to avoid switch-
ing currents caused by floating inputs. The T0CKI input
should also be at V
on-chip pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (V
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR pin low.
FIGURE 6-12:
DS35007B-page 32
Note
(INTCON<1>)
(INTCON<7>)
INSTRUCTION FLOW
CLKOUT
Instruction
Instruction
INTF Flag
Executed
Fetched
INT pin
GIE bit
OSC1
1:
2:
3:
4:
Power-down Mode (SLEEP)
PC
(4)
XT, HS, or LP oscillator mode assumed.
T
GIE = ’1’ assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
SLEEP
OST
Inst(PC) = SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
= 1024T
Inst(PC - 1)
PC
DD
OSC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
or V
(drawing not to scale). This delay will not be there for RC osc mode.
DD
SS
Inst(PC + 1)
or V
. The contribution from
SLEEP
PC+1
SS
, with no external
Processor in
SLEEP
IHMC
PC+2
).
T
OST
(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC + 2)
Inst(PC + 1)
6.11.2
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
Peripherals cannot generate interrupts during SLEEP,
since no on-chip Q clocks are present.
The first event (MCLR Reset) will cause a device
RESET. The two latter events are considered a contin-
uation of program execution. The TO and PD bits can
be used to determine the cause of a device RESET.
The PD bit, which is set on power-up, is cleared when
SLEEP is invoked. The TO bit is cleared if a WDT
time-out occurred (and caused wake-up).
While the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up
occurs regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
the instruction after the SLEEP instruction. If the GIE bit
is set (enabled), the device executes the instruction
after the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the
execution of the instruction following SLEEP is not
desirable, the user should have a NOP after the
SLEEP instruction.
PC+2
External RESET input on MCLR pin.
WDT wake-up (if WDT was enabled).
Interrupt from RB0/INT pin, RB port change, or
data EEPROM write complete.
Interrupt Latency
Dummy cycle
WAKE-UP FROM SLEEP
(Note 2)
PC + 2
2001 Microchip Technology Inc.
Dummy cycle
Inst(0004h)
0004h
Inst(0005h)
Inst(0004h)
0005h