PIC16C71-04/P Microchip Technology, PIC16C71-04/P Datasheet - Page 54

• Manufacturer Part Number: PIC16C71-04/P
• Description: IC MCU OTP 1KX14 A/D 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C71-04/P

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Type: OTP
• Ram Size: 36 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 4x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16C
• No. Of I/o's: 13
• Ram Memory Size: 36Byte
• Cpu Speed: 4MHz
• No. Of Timers: 1
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 36 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 4 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 309-1059 - ADAPTER 18 ZIF BD W/18SO PLUGSDVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

PIC16C71X
8.4.5
On power-up the time-out sequence is as follows: First
PWRT time-out is invoked after the POR time delay has
expired. Then OST is activated. The total time-out will
vary based on oscillator configuration and the status of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 8-11,
Figure 8-12,
sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 8-12). This is useful for testing purposes or to
synchronize more than one PIC16CXX device operat-
ing in parallel.
Table 8-10 and Table 8-11 show the reset conditions for
some special function registers, while Table 8-12 and
Table 8-13 show the reset conditions for all the
registers.
8.4.6
The Power Control/Status Register, PCON has up to
two bits, depending upon the device.
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent resets to see if bit
BOR cleared, indicating a BOR occurred. The BOR bit
is a "Don’t Care" bit and is not necessarily predictable
if the Brown-out Reset circuitry is disabled (by clearing
bit BODEN in the Configuration Word).
TABLE 8-5:
TABLE 8-6:
DS30272A-page 54
Applicable Devices
Applicable Devices
Oscillator Configuration
Oscillator Configuration
XT, HS, LP
TIME-OUT SEQUENCE
POWER CONTROL/STATUS REGISTER
(PCON)
XT, HS, LP
RC
and
RC
TIME-OUT IN VARIOUS SITUATIONS, PIC16C71
TIME-OUT IN VARIOUS SITUATIONS, PIC16C710/711/715
Figure 8-13
710 71 711 715
710 71 711 715
72 ms + 1024T
PWRTE = 0
72 ms
depict
72 ms + 1024T
PWRTE = 1
Power-up
OSC
72 ms
time-out
PWRTE = 1
1024T
OSC
Power-up
—
OSC
Bit1 is POR (Power-on Reset Status bit). It is cleared
on a Power-on Reset and unaffected otherwise. The
user must set this bit following a Power-on Reset.
For the PIC16C715, bit2 is PER (Parity Error Reset). It
is cleared on a Parity Error Reset and must be set by
user software. It will also be set on a Power-on Reset.
For the PIC16C715, bit7 is MPEEN (Memory Parity
Error Enable). This bit reflects the status of the MPEEN
bit in configuration word. It is unaffected by any reset of
interrupt.
8.4.7
The PIC16C715 has on-chip parity bits that can be
used to verify the contents of program memory. Parity
bits may be useful in applications in order to increase
overall reliability of a system.
There are two parity bits for each word of Program
Memory. The parity bits are computed on alternating
bits of the program word. One computation is per-
formed using even parity, the other using odd parity. As
a program executes, the parity is verified. The even par-
ity bit is XOR’d with the even bits in the program mem-
ory word. The odd parity bit is negated and XOR’d with
the odd bits in the program memory word. When an
error is detected, a reset is generated and the PER flag
bit 2 in the PCON register is cleared (logic ‘0’). This indi-
cation can allow software to act on a failure. However,
there is no indication of the program memory location
of the failure in Program Memory. This flag can only be
set (logic ‘1’) by software.
The parity array is user selectable during programming.
Bit 7 of the configuration word located at address
2007h can be programmed (read as ‘0’) to disable par-
ity. If left unprogrammed (read as ‘1’), parity is enabled.
Applicable Devices
PWRTE = 0
1024T
72 ms + 1024T
PARITY ERROR RESET (PER)
—
Brown-out
OSC
72 ms
OSC
1997 Microchip Technology Inc.
710 71 711 715
Wake-up from SLEEP
Wake-up from SLEEP
1024 T
1024T
—
OSC
—
OSC