PIC18F4420-I/ML Microchip Technology, PIC18F4420-I/ML Datasheet - Page 14

• Manufacturer Part Number: PIC18F4420-I/ML
• Description: IC MCU FLASH 8KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4420-I/ML

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: MSSP, SPI, I2C, PSP, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13 bit
• Package: 44QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / Rohs Status: Details

PIC18F2XXX/4XXX FAMILY
3.0
Programming includes the ability to erase or write the
various memory regions within the device.
In all cases, except high-voltage ICSP Bulk Erase, the
EECON1 register must be configured in order to
operate on a particular memory region.
When using the EECON1 register to act on code
memory, the EEPGD bit must be set (EECON1<7> = 1)
and the CFGS bit must be cleared (EECON1<6> = 0).
The WREN bit must be set (EECON1<2> = 1) to
enable writes of any sort (e.g., erases) and this must be
done prior to initiating a write sequence. The FREE bit
must be set (EECON1<4> = 1) in order to erase the
program space being pointed to by the Table Pointer.
The erase or write sequence is initiated by setting the
WR bit (EECON1<1> = 1). It is strongly recommended
that the WREN bit only be set immediately prior to a
program erase.
3.1
3.1.1
Erasing code or data EEPROM is accomplished by
configuring two Bulk Erase Control registers located at
3C0004h and 3C0005h. Code memory may be erased,
portions at a time, or the user may erase the entire
device in one action. Bulk Erase operations will also
clear any code-protect settings associated with the
memory block being erased. Erase options are detailed
in
(CPD = 0), the user must request an erase of data
EEPROM (e.g., 0084h as shown in
TABLE 3-1:
DS39622L-page 14
Chip Erase
Erase Data EEPROM
Erase Boot Block
Erase Configuration Bits
Erase Code EEPROM Block 0
Erase Code EEPROM Block 1
Erase Code EEPROM Block 2
Erase Code EEPROM Block 3
Erase Code EEPROM Block 4
Erase Code EEPROM Block 5
Note 1:
Table
DEVICE PROGRAMMING
ICSP Erase
3-1. If data EEPROM is code-protected
Description
Selected devices only, see
“Data EEPROM
HIGH-VOLTAGE ICSP BULK ERASE
BULK ERASE OPTIONS
(1)
Programming”.
(3C0005h:3C0004h)
Table
Section 3.3
3F8Fh
0084h
0081h
0082h
0180h
0280h
0480h
0880h
1080h
2080h
Data
3-1).
The actual Bulk Erase function is a self-timed
operation. Once the erase has started (falling edge of
the 4th PGC after the NOP command), serial execution
will cease until the erase completes (Parameter P11).
During this time, PGC may continue to toggle but PGD
must be held low.
The code sequence to erase the entire device is shown
in
TABLE 3-2:
FIGURE 3-1:
Command
Table 3-2
Note:
0000
0000
0000
0000
0000
0000
1100
0000
0000
0000
0000
0000
0000
1100
0000
0000
4-Bit
A Bulk Erase is the only way to reprogram
code-protect bits from an ON state to an
OFF state.
and the flowchart is shown in
Payload
0E 3C
6E F8
0E 00
6E F7
0E 05
6E F6
3F 3F
0E 3C
6E F8
0E 00
6E F7
0E 04
6E F6
8F 8F
00 00
00 00
Data
BULK ERASE COMMAND
SEQUENCE
3C0004h to Erase
Delay P11 + P10
Write 8F8Fh to
Entire Device
Write 3F3Fh
to 3C0005h
BULK ERASE FLOW
 2010 Microchip Technology Inc.
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 05h
MOVWF TBLPTRL
Write 3F3Fh to 3C0005h
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 04h
MOVWF TBLPTRL
Write 8F8Fh TO 3C0004h
to erase entire
device.
NOP
Hold PGD low until
erase completes.
Done
Time
Start
Core Instruction
Figure
3-1.