AT89C5122D-PSTUM Atmel, AT89C5122D-PSTUM Datasheet - Page 124

• Manufacturer Part Number: AT89C5122D-PSTUM
• Description: IC 8051 MCU FLASH 32K 64QFN
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C5122D-PSTUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: SmartCard, SPI, UART/USART, USB
• Peripherals: LED, POR, WDT
• Number Of I /o: 46
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFN
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-03 - KIT STARTER FOR MCU AT8XC5122/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Serial I/O Port
Framing Error Detection
124
AT83R5122, AT8xC5122/23
The serial I/O port in the AT83R5122, AT8xC5122/23 is compatible with the serial I/O
port in the 80C52.
The I/O port provides both synchronous and asynchronous communication modes. It
operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-
duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur
simultaneously and at different baud rates
Serial I/O port includes the following enhancements:
•
•
Framing bit error detection is provided for the three asynchronous modes (Modes 1, 2
and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON regis-
ter (See Figure 64).
Figure 64. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register (See Figure 69 on page 128) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a reset can clear FE bit. Subsequently received frames with valid stop
bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the
last data bit (See Figure 65 and Figure 66).
Figure 65. UART Timings in Mode 1
Framing error detection
Automatic address recognition
SMOD0=X
SMOD0=1
RXD
SM0/FE
SMOD1
FE
RI
SMOD0
SM1
Start
Bit
SM2
D0
-
D1
REN
Set FE Bit if Stop Bit is 0 (Framing Error) (SMOD0 = 1)
SM0 to UART Mode Control (SMOD0 = 0)
POF
To UART Framing Error Control
D2
TB8
GF1
D3
Data Byte
RB8
GF0
D4
D5
PD
TI
D6
IDL
RI
D7
SCON (98h)
PCON (87h)
Stop
Bit
4202F–SCR–07/2008