PIC18LF2331-I/SO Microchip Technology, PIC18LF2331-I/SO Datasheet - Page 3

• Manufacturer Part Number: PIC18LF2331-I/SO
• Description: IC MCU FLASH 4KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2331-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

10. Module: Program Memory
11. Module: Core (DAW Instruction)
EXAMPLE 1:
© 2005 Microchip Technology Inc.
MOVLW
ADDLW
BTFSC
INCFSZ byte2
DAW
BTFSC
INCFSZ byte2
This is repeated for each DAW instruction.
When writing to the program memory, the contents
of the program memory may not be written as
expected if the internal voltage reference is not
enabled.
Work around
Either of two workarounds can be used:
1. Before beginning any writes to the program
2. Configure the BOR as enabled (any voltage).
Date Codes that pertain to this issue:
All engineering and production devices.
The DAW instruction may improperly clear the
Carry bit (Status<0>) when executed.
Work around
Test the Carry bit state before executing the DAW
instruction. If the Carry bit is set, increment the
next higher byte to be added, using an instruction
such as INCFSZ (this instruction does not affect
any Status flags and will not overflow a BCD
nibble). After the DAW instruction has been
executed, process the Carry bit normally (see
Example 1).
Date Codes that pertain to this issue:
All engineering and production devices.
memory, enable the LVD (any voltage) and
wait for the internal voltage reference to
become stable. LVD interrupt requests may be
ignored. Once the LVD voltage reference is
stable, perform all program memory writes nor-
mally. When writes have been completed, the
LVD may be disabled.
Select a threshold below V
operation. If V
the device will be held in BOR Reset.
0x80
0x80
STATUS, C
STATUS, C
BIT DURING BCD ADDITIONS
PROCESSING THE CARRY
DD
; .80 (BCD)
; .80 (BCD)
; test C
; inc next higher LSB
; test C
; inc next higher LSB
is below the BOR threshold,
DD
to allow normal
PIC18F2331/2431/4331/4431
12. Module: EUSART
13. Module: EUSART
14. Module: EUSART
15. Module: EUSART
16. Module: EUSART
Bit SENDB in the TXSTA register is not automati-
cally cleared by hardware upon completion of
transmission of a Sync Break.
Work around
Check the TRMT bit in TXSTA. If the TRMT bit is
set, Break transmission is said to be complete.
If the transmitter is left enabled while the module is
performing an auto-baud operation, an arbitrary
data byte may get transmitted.
Work around
Clear TXEN (TXSTA<5>) before any auto-baud
operation and set it after auto-baud is complete.
Enable TXEN only when a data byte is to be
transmitted. Care must be taken to ensure that the
TX pin is pulled high, either through an external
resistor, or by making the TX pin an output and
writing ‘1’ to it to not disturb the transmit line.
This module may perform incorrect auto-baud
calculation if the ABDEN (BAUDCON<0>) bit was
set while the receive pin was at a low level.
Work around
Wait for the RX pin to go high and then set the
ABDEN bit.
In Asynchronous Receiver mode, the EUSART
does not load the SPBRGH value after completion
of auto-baud.
Work around
Do not enable the BRG16 (BAUDCON<3>) bit.
If the BRG16 is in use, ensure that the auto-baud
SPBRG value does not exceed the 8-bit value.
The CREN (RCSTA<4>) bit is cleared after every
auto-baud operation.
Work around
Upon completion of auto-baud, manually set the
CREN bit.
DS80180C-page 3