PIC18LF2331-I/SO Microchip Technology, PIC18LF2331-I/SO Datasheet - Page 3

• Manufacturer Part Number: PIC18LF2331-I/SO
• Description: IC MCU FLASH 4KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2331-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

10. Module: EUSART
11. Module: EUSART
12. Module: EUSART
13. Module: EUSART
© 2005 Microchip Technology Inc.
This module may perform incorrect auto-baud
calculation if the ABDEN (BAUDCTL<0>) bit was
set while the receive pin was at a low level.
Work around
Wait for the RX pin to go high and then set the
ABDEN bit.
In Asynchronous Receiver mode, the EUSART
does not load the SPBRGH value after completion
of auto-baud.
Work around
Do not enable the BRG16 (BAUDCTL<3>) bit.
If the BRG16 is in use, ensure that the auto-baud
SPBRG value does not exceed the 8-bit value.
The CREN (RCSTA<4>) bit is cleared after every
auto-baud operation.
Work around
Upon completion of auto-baud, manually set the
CREN bit.
Writing to the USART/EUSART TXREG register
faster than the baud rate in Synchronous mode
will overwrite the previous value instead of
double-buffering, as in Asynchronous mode.
Work around
Load the first character into TXREG and then wait
for a TX interrupt, or check the TXIF bit before
writing each additional character to TXREG.
PIC18F2331/2431/4331/4431
14. Module: EUSART
15. Module: HSADC
The EUSART cannot receive asynchronous data at
the four fastest baud rates (BRGH = 1, BRG16 = 1
and SPBRG < 4).
Work around
Use a slower baud rate or a faster system clock
speed.
A ΔI
(for V
put into Sleep mode with the HSADC enabled
(ADON = 1) without setting the GO/DONE bit so
that at least one conversion is performed.
Observed ΔI
Work around
If no conversion will be done while in Sleep mode,
disable the HSADC module by clearing the ADON
bit before entering Sleep mode.
If power consumption is an issue for the
application, do not put the part into Sleep mode
with the HSADC enabled if no conversion is to be
performed.
AD
DD
(parameter D026) of greater than 300 μA
= 3V) is observed when the device is
AD
will increase in proportion to V
DS80192C-page 3
DD
.