PIC18F4520-I/P Microchip Technology, PIC18F4520-I/P Datasheet

IC MCU FLASH 16KX16 40DIP

PIC18F4520-I/P

Manufacturer Part Number
PIC18F4520-I/P
Description
IC MCU FLASH 16KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F4520-I/P

Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
MSSP, SPI, I2C, PSP, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, 53275-917, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
13 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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0
The PIC18F2420/2520/4420/4520 Rev. A1 parts you
have received conform functionally to the Device Data
Sheet
described below. Any Data Sheet Clarification issues
related to the PIC18F2420/2520/4420/4520 will be
reported in a separate Data Sheet errata. Please check
the Microchip web site for any existing issues.
All the problems listed here will be addressed in future
revisions of the PIC18F2420/2520/4420/4520 silicon.
The
PIC18F2420/2520/4420/4520 devices with these
Device/Revision IDs:
TABLE 1:
© 2008 Microchip Technology Inc.
The Device IDs (DEVID1 and DEVID2) are located at
addresses
configuration space. They are shown in binary in the
format “DEVID2 DEVID1”.
Note 1:
Part Number
PIC18F2420
PIC18F2520
PIC18F4420
PIC18F4520
PIC18F2420/2520/4420/4520 Rev. A1 Silicon Errata Sheet
following
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
(DS39631D),
4 MHz
4 MHz
4 MHz
F
OSC
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
3FFFFEh:3FFFFFh
I
2
2
C™ interface does not conform to the 400 kHz I
C™ CLOCK RATE w/BRG
silicon
0001 0001 010
0001 0001 000
0001 0000 110
0001 0000 100
Device ID
except
errata apply
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
for
F
CY
in
the
PIC18F2420/2520/4420/4520
Revision ID
the
0 0001
0 0001
0 0001
0 0001
anomalies
only
device’s
to
20 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
CY
* 2
1. Module: MSSP
2
C specification (which applies to rates greater than
In its current implementation, the I
mode operates as follows:
a) The Baud Rate Generator for I
b) Use the following formula in place of the one
Date Codes that pertain to this issue:
All engineering and production devices.
mode is slower than the rates specified in
Table 17-3 of the Device Data Sheet.
For this revision of silicon, use the values
shown in Table 1 in place of those shown in
Table 17-3 of the Device Data Sheet. The
differences are shown in bold text.
shown in Register 17-4 (SSPCON1) of the
Device
SSPM3:SSPM0 = 1000.
SSPADD = INT((F
BRG Value
Data
0Eh
15h
59h
05h
08h
23h
01h
08h
00h
Sheet
CY
/F
SCL
(2 Rollovers of BRG)
) – (F
for
CY
400 kHz
400 kHz
333 kHz
312.5 kHz
DS80209H-page 1
1 MHz
bit
100 kHz
308 kHz
100 kHz
100 kHz
/1.111 MHz)) – 1
F
2
2
SCL
C in Master
C™ Master
description
(1)
(1)
(1)
(1)

Related parts for PIC18F4520-I/P

PIC18F4520-I/P Summary of contents

Page 1

... Device/Revision IDs: Part Number Device ID PIC18F2420 0001 0001 010 PIC18F2520 0001 0001 000 PIC18F4420 0001 0000 110 PIC18F4520 0001 0000 100 The Device IDs (DEVID1 and DEVID2) are located at addresses 3FFFFEh:3FFFFFh in configuration space. They are shown in binary in the format “DEVID2 DEVID1”. 2 ...

Page 2

... Wait for the system to become idle before setting the RCEN bit. This requires a check for the following bits to be clear: ACKEN, RCEN, PEN, RSEN and SEN. Date Codes that pertain to this issue: All engineering and production devices. © 2008 Microchip Technology Inc. ...

Page 3

... Work around None. Date Codes that pertain to this issue: All engineering and production devices. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 9. Module: ECCP and CCP The CCP1 and CCP2 configured for PWM mode, with 1:1 Timer2 prescaler and duty cycle set to the period minus 1, may result in the PWM output(s) remaining at a logic low level ...

Page 4

... Event Trigger Reset of the timer occurs on the next prescaler output pulse after the match between TMRxH:TMRxL and CCPR1H:CCPR1L. Work around To achieve the same timer Reset period on the PIC18F4520 family as the PIC18F452 family for a given clock source, add 1 to the value in CCPR1H:CCPR1L. In other ...

Page 5

... BORV1:BORV0 = 11 N/A 2.05 N/A Work around Use the next higher BOD voltage setting to ensure a low V is detected above 2.0V. DD Date Codes that pertain to this issue: All engineering and production devices. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 + and V - REF REF PIC18LFX42X/X52X (INDUSTRIAL) Min ...

Page 6

... TMR1H/TMR3H was written. Work around Two work arounds are available: 1) Stop Timer1/ Timer3 before writing the registers; 2) Write TMR1L/TMR3L immediately after writing TMR1H/TMR3H. Date Codes that pertain to this issue: All engineering and production devices. © 2008 Microchip Technology Inc. TMR1H/TMR3H ...

Page 7

... Foo call : ; insert high priority ISR code here : RETFIE FAST © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Work around 1. Assembly Language Programming any two-cycle instruction is used to modify the WREG, BSR or STATUS register, do not use the RETFIE FAST instruction to return from the interrupt ...

Page 8

... RETFIE FAST instruction. If the proper high priority interrupt bit is set in the IPRx register, then the interrupt is treated as high priority in spite of the pragma interruptlow directive. C18 C Compiler, The code segment shown in Example 3 demonstrates the work around using the C18 This compiler: © 2008 Microchip Technology Inc. ...

Page 9

... still set, the slave should read SSPBUF and clear SSPOV. Discard the data from SSPBUF. Date Codes that pertain to this issue: All engineering and production devices. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 28. Module: MSSP Master mode, the BRG value of ‘0’ may not work correctly ...

Page 10

... Set up the timer to overflow at the end of the Stop bit, then start the timer when you load the TXREG. Do not load the TXREG when timer is about to overflow. Date Codes that pertain to this issue: All engineering and production devices. © 2008 Microchip Technology Inc. ...

Page 11

... Poll the WUE bit and read RCREG after the WUE bit is automatically cleared. Date Codes that pertain to this issue: All engineering and production devices. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 37. Module: MSSP The MSSP configured in SPI Slave mode will generate a write collision if SSPBUF is updated and ...

Page 12

... Work around Select the AD clock source and avoid selecting OSC OSC OSC RC. OSC Date Codes that pertain to this issue: All engineering and production devices. © 2008 Microchip Technology Inc. or OSC , OSC OSC ...

Page 13

... Change the 7-bit slave address in SSPADD to an address in the range of 0x08 to 0x77. • Use Revision B silicon This version of silicon removes this issue’s addressing restrictions. Date Codes that pertain to this issue: All engineering and production devices. © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 Slave mode DS80209H-page 13 ...

Page 14

... Removed previous issue 33 (Timer1 – Asynchronous Counter). Added issues 33-36 (EUSART), 37-40 (MSSP), 41 (Timer1) and 42 (Reset). Rev F Document (3/2007) Revised issue 27 (MSSP). Rev G Document (6/2007) Added silicon issue 43 (10-Bit Analog-to-Digital Converter). Rev H Document (1/2008) 2 Added silicon issue 44 (MSSP – Slave). DS80209H-page 14 © 2008 Microchip Technology Inc. ...

Page 15

... PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 16

... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...

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