AT89C5122D-RDRUM Atmel, AT89C5122D-RDRUM Datasheet - Page 121

• Manufacturer Part Number: AT89C5122D-RDRUM
• Description: IC 8051 MCU 32K CRAM USB 64-VQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C5122D-RDRUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: SmartCard, SPI, UART/USART, USB
• Peripherals: LED, POR, WDT
• Number Of I /o: 46
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-03 - KIT STARTER FOR MCU AT8XC5122/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: AT89C5122D-RDRUMTR

4202F–SCR–07/2008
Table 73. USB Endpoint FIFO Reset Register - UEPRST (S:D5h)
Reset Value = 0000 0000b
Number
Bit
7
6
5
4
3
2
1
0
7
-
Mnemonic Description
EP6RST
EP5RST
EP4RST
EP3RST
EP2RST
EP1RST
EP0RST
EP6RST
Bit
-
6
Reserved
The value read from these bits is always 0. Do not change this bit.
Endpoint 6 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 5 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 4 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 3 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 2 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 1 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 0 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
EP5RST
5
EP4RST
AT83R5122, AT8xC5122/23
4
EP3RST
3
EP2RST
2
EP1RST
1
EP0RST
0
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