IC DSPIC MCU/DSP 128K 64TQFP

DSPIC33FJ128GP206-I/PT

Manufacturer Part NumberDSPIC33FJ128GP206-I/PT
DescriptionIC DSPIC MCU/DSP 128K 64TQFP
ManufacturerMicrochip Technology
SeriesdsPIC™ 33F
DSPIC33FJ128GP206-I/PT datasheets
 

Specifications of DSPIC33FJ128GP206-I/PT

Program Memory TypeFLASHProgram Memory Size128KB (128K x 8)
Package / Case64-TFQFPCore ProcessordsPIC
Core Size16-BitSpeed40 MIPs
ConnectivityI²C, IrDA, LIN, SPI, UART/USARTPeripheralsAC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o53Ram Size8K x 8
Voltage - Supply (vcc/vdd)3 V ~ 3.6 VData ConvertersA/D 18x10b/12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
ProductDSCsData Bus Width16 bit
Processor SeriesDSPIC33FCoredsPIC
Maximum Clock Frequency40 MHzNumber Of Programmable I/os53
Data Ram Size8 KBMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By SupplierPG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033Minimum Operating Temperature- 40 C
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With876-1001 - DSPIC33 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size-  
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dsPIC33F
Product Overview
®
dsPIC
DSC High-Performance 16-Bit
Digital Signal Controllers
Preliminary
© 2005 Microchip Technology Inc.
DS70155C

DSPIC33FJ128GP206-I/PT Summary of contents

  • Page 1

    ... Microchip Technology Inc. Product Overview ® DSC High-Performance 16-Bit Digital Signal Controllers Preliminary dsPIC33F DS70155C ...

  • Page 2

    ... PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

  • Page 3

    ... CPU is executing code (no cycle stealing) • dual-ported DMA buffer area (DMA RAM) to store data transferred via DMA • Most peripherals support DMA © 2005 Microchip Technology Inc. dsPIC33F Interrupt Controller • 5-cycle latency • 117 interrupt vectors • available interrupt sources external interrupts • ...

  • Page 4

    ... Industrial temperature • Low-power consumption Packaging: • 100-pin TQFP (14x14x1 mm and 12x12x1 mm) • 80-pin TQFP (12x12x1 mm) • 64-pin TQFP (10x10x1 mm) Note: See Table 1-1 and Table 1-2 for exact peripheral features per device. Preliminary © 2005 Microchip Technology Inc. ...

  • Page 5

    ... Note 1: RAM size is inclusive DMA RAM. 2: Maximum I/O pin count includes pins shared by the peripheral functions. © 2005 Microchip Technology Inc. (1) RAM ( A/D, ...

  • Page 6

    ... Supply (UPS), inverters, Switched mode power supplies, power factor correction and also for controlling the power management module in servers, telecommunication equipment and other industrial equipment Preliminary Packages © 2005 Microchip Technology Inc. ...

  • Page 7

    ... TQFP (Thin Quad Flatpack 14x14 mm TQFP (Thin Quad Flatpack) Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise Engineering Sample © 2005 Microchip Technology Inc. Examples: a) dsPIC33FJ256GP710I/PT-PS: General Purpose dsPIC33 program memory, 100-pin, Industrial temp., TQFP package, Prototype Sample. b) ...

  • Page 8

    ... X AGU Program Flash Memory Data Access Program Counter Program <23 bits> 23 Memory Instruction 256 Kbytes Prefetch & Decode 24 Dual Port Status Register 2 Kbytes Preliminary program memory ensures up to I/O Ports Flash Peripherals up to RAM DMA Controller © 2005 Microchip Technology Inc. ...

  • Page 9

    ... The data space includes 2 Kbytes of DMA RAM, which is primarily used for DMA data transfers, but may be used as general purpose RAM. © 2005 Microchip Technology Inc. FIGURE 3-1: predictable of which are ...

  • Page 10

    ... Linear indirect access of 32K word (64 Kbyte) pages within program space is possible, using any working register via new table read and write instructions. 6. Part of data space can be mapped into program space, allowing constant data to be accessed were in data space. Preliminary © 2005 Microchip Technology Inc. ...

  • Page 11

    ... Least and Most Significant Bytes can be manipulated through byte-wide data memory space accesses. © 2005 Microchip Technology Inc. W15 is the dedicated software Stack Pointer (SP automatically modified by exception processing and subroutine calls and returns. However, W15 can be referenced by any instruction in the same manner as all other W registers ...

  • Page 12

    ... SRL Preliminary Legend: PUSH.S Shadow DO Shadow Working Registers *W15 and SPLIM not shadowed Stack Pointer Limit Register 0 Program Counter REPEAT Loop Counter DO Loop Counter DO Loop Start Address DO Loop End Address Core Configuration Register Z C Status Register © 2005 Microchip Technology Inc. ...

  • Page 13

    ... CPU is given precedence in accessing the DMA RAM location. Therefore, the DMA RAM provides a reliable means of transferring DMA data without ever having to stall the CPU. © 2005 Microchip Technology Inc. 3.3.3 DATA SPACE WIDTH The core data width is 16 bits. All internal registers are organized as 16-bit wide words ...

  • Page 14

    ... LSB 0x0001 SFR Space 0x07FF 0x0801 X Data RAM (X) 0x3FFF 0x4001 Y Data RAM (Y) 0x77FF 0x7801 DMA RAM 0x7FFF 0x8001 X Data Unimplemented (X) 0xFFFF Preliminary Least Significant Byte Address 0x0000 0x07FE 0x0800 0x3FFE 0x4000 0x77FE 0x7800 0x7FFE 0x8000 0xFFFE © 2005 Microchip Technology Inc. ...

  • Page 15

    ... Overflow into guard bits 32 through 39. This is a recoverable overflow. This bit (OA/OB) is set whenever all the guard bits are not identical to each other. © 2005 Microchip Technology Inc. 3.4.3 SATURATION AND OVERFLOW The adder has an additional saturation block that controls accumulator data saturation, if selected. It ...

  • Page 16

    ... FIGURE 3-4: DSP ENGINE BLOCK DIAGRAM 40 DS70155C-page 14 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler Operand Latches 16 16 To/From W Array Preliminary Round u r Logic Enable 16 Zero Backfill © 2005 Microchip Technology Inc. ...

  • Page 17

    ... CPU Ready Peripheral Note: CPU and DMA address buses are not shown for clarity. © 2005 Microchip Technology Inc. • Indirect addressing of DMA RAM locations with or without automatic post-increment • Peripheral Indirect Addressing – In some peripherals, the DMA RAM read/write addresses may be partially derived from the peripheral • ...

  • Page 18

    ... DMA2 – DMA Channel 2 0x000146 OC3 – Output Compare 3 0x000148 OC4 – Output Compare 4 0x00014A T4 – Timer4 0x00014C T5 – Timer5 0x00014E INT2 – External Interrupt 2 0x000150 U2RX – UART2 Receiver 0x000152 U2TX – UART2 Transmitter Preliminary Interrupt Source © 2005 Microchip Technology Inc. ...

  • Page 19

    ... Microchip Technology Inc. AIVT Address 0x000154 SPI2E – SPI2 Error 0x000156 SPI1D – SPI1 Transfer Done 0x000158 C1RX – ECAN1 Receive Data Ready 0x00015A C1 – CAN1 Event 0x00015C DMA3 – DMA Channel 3 0x00015E IC3 – ...

  • Page 20

    ... AIVT Address 0x000004 0x000084 0x000006 0x000086 0x000008 0x000088 0x00000A 0x00008A 0x00000C 0x00008C 0x00000E 0x00008E 0x000010 0x000090 0x000012 0x000092 Preliminary Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error DMA Error Trap Reserved Reserved © 2005 Microchip Technology Inc. ...

  • Page 21

    ... Another scaled reference clock is used by the Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). © 2005 Microchip Technology Inc. The clock signals generated by the FRC and primary oscillators can be optionally applied to an on-chip Phase Locked Loop (PLL) to provide a wide range of output frequencies for device operation ...

  • Page 22

    ... PM3 Programmer) allows programming of this and other configuration bits to the desired state. If enabled, the WDT increments until it overflows or “times out”. A time is OST WDT time-out forces a device Reset (except during Sleep). Preliminary OSC Divide Timer1 ® © 2005 Microchip Technology Inc. ...

  • Page 23

    ... The trap can be treated as a warm Reset by simply loading the Reset address into the oscillator fail trap vector. © 2005 Microchip Technology Inc. 6.6 Reset System The Reset system combines all Reset sources and controls the device Master Reset signal ...

  • Page 24

    ... This feature further reduces the power consumption during periods where relatively less CPU activity is required. When the device is operating in Doze mode, the hardware synchronization between peripheral events and SFR accesses by the CPU. Preliminary IDLE MODE DOZE MODE ensures that there is no loss © 2005 Microchip Technology Inc. of ...

  • Page 25

    ... External V + and V - pins available REF REF • ±1 LSB max Differential Nonlinearity (DNL) (3.3V ±10%) © 2005 Microchip Technology Inc. • ±1 LSB max Integral Nonlinearity (INL) (3.3V ±10%) • on-chip sample and hold amplifiers in each A/D functions - Enables simultaneous sampling analog inputs • ...

  • Page 26

    ... In particular, the following power and motion control applications are supported: • Three-Phase AC Induction Motor • Switched Reluctance (SR) Motor • Brushless DC (BLDC) Motor • Uninterrupted Power Supply (UPS) Preliminary TSYNC Sync 1 0 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2005 Microchip Technology Inc. ...

  • Page 27

    ... MHz) 200 ns (5 MHz) 200 ns (5 MHz) * PWM frequencies will be 1/2 the value indicated for center-aligned operation. © 2005 Microchip Technology Inc. 8.3.1 PWM TIME BASE The PWM time base is provided by a 15-bit timer with a prescaler and postscaler. The PWM time base can be configured for four different modes of operation: • ...

  • Page 28

    ... PWM Generator Channel 2 Dead-Time #2 Generator and Override Logic PWM Generator Channel 1 Dead-Time #1 Generator and Override Logic Special Event Postscaler PTDIR Preliminary PWM4H PWM4L PWM3H PWM3L Output Driver Block PWM2H PWM2L PWM1H PWM1L FLTA FLTB Special Event Trigger © 2005 Microchip Technology Inc. ...

  • Page 29

    ... Existing Pin Logic 0 UPDN Up/Down 1 © 2005 Microchip Technology Inc. increment when the shaft is rotating one direction and decrement when the shaft is rotating in the other direction. The QEI module (Figure 8-3) includes: • Three input pins for two phase signals and index systems ...

  • Page 30

    ... Long data word lengths can be supported by the DCI. The DCI is configured to transmit/receive the long word in multiple 16-bit time slots. This operation is transparent to the user and the long data word is stored in consecutive register locations. Preliminary © 2005 Microchip Technology Inc. ...

  • Page 31

    ... FSYNC (Frame Synchronization Pulse). A device set SPI master provides the serial communication clock signal on its SCK pin. © 2005 Microchip Technology Inc. bits for each time slot in the data frame that determine whether the DCI will transmit/receive during the time slot ...

  • Page 32

    ... Status and errors can be checked by reading the appropriate registers. Any message detected on the CAN bus is checked for errors and then matched against filters port can be see if it should be received and stored in one of the receive registers. Preliminary © 2005 Microchip Technology Inc. ...

  • Page 33

    ... This can be used in read-modify-write instructions that allow the user to modify the contents of the Port Data Latch register, regardless of the status of the corresponding pins. © 2005 Microchip Technology Inc. The I/O pins have the following features: • Schmitt Trigger input • CMOS output drivers • ...

  • Page 34

    ... Table 9-9. These instructions require two words of Table 9-3 memory because their opcodes embed large literal operands. Table 9-4 Table 9-5 Table 9-6 Table 9-7 Table 9-8 Table 9-9 Table 9-10 Table 9-11 Table 9-12 Preliminary © 2005 Microchip Technology Inc. ...

  • Page 35

    ... Source addressing mode and working register for X data bus prefetch Wx Destination working register for X data bus prefetch Wxd Source addressing mode and working register for Y data bus prefetch Wy Destination working register for Y data bus prefetch Wyd © 2005 Microchip Technology Inc. Description Preliminary dsPIC33F DS70155C-page 33 ...

  • Page 36

    ... Move Wns to [Wd + signed 10-bit offset] Move Move double Ws to Wnd:Wnd + 1 Move double Wns:Wns + byte or nibble swap Wn Read high program word to Wd Read low program word to Wd Write Ws to high program word Write Ws to low program word Preliminary Words Cycles © 2005 Microchip Technology Inc. ...

  • Page 37

    ... SUBR f {,WREG} SUBR Wb,#lit5,Wd SUBR Wb,Ws,Wd ZE Ws,Wnd * Divide instructions are interruptible on a cycle-by-cycle basis. Also, divide instructions must be accompanied by a REPEAT instruction, which adds 1 extra cycle. © 2005 Microchip Technology Inc. Description Destination = f + WREG Wn = lit10 + lit5 Destination = f + WREG + ( lit10 + lit5 + ( ( decimal adjust Wn Destination = f – ...

  • Page 38

    ... Destination = f .AND. WREG Wn = lit10 .AND .AND. lit5 .AND 0x0000 WREG = 0x0000 Wd = 0x0000 Destination = Destination = f .IOR. WREG Wn = lit10 .IOR .IOR. lit5 .IOR. Ws Destination = 0xFFFF WREG = 0xFFFF Wd = 0xFFFF Destination = f .XOR. WREG Wn = lit10 .XOR .XOR. lit5 .XOR. Ws Preliminary Words Cycles © 2005 Microchip Technology Inc. ...

  • Page 39

    ... FF1L Ws,Wnd FF1R Ws,Wnd Note: Bit positions are specified by bit4 (0:15) for word operations. © 2005 Microchip Technology Inc. Description Destination = arithmetic right shift arithmetic right shift Ws Wnd = arithmetic right shift Wb by lit4 Wnd = arithmetic right shift Wb by Wns Destination = logical right shift f ...

  • Page 40

    ... Bit positions are specified by bit4 (0:15) for word operations. 2: Conditional skip instructions execute in 1 cycle if the skip is not taken, 2 cycles if the skip is taken over a one-word instruction and 3 cycles if the skip is taken over a two-word instruction. DS70155C-page 38 Description Preliminary © 2005 Microchip Technology Inc. Words Cycles ...

  • Page 41

    ... Note 1: Conditional branch instructions execute in 1 cycle if the branch is not taken cycles if the branch is taken. 2: RETURN normally executes in 3 cycles; however, it executes in 2 cycles if an interrupt is pending. © 2005 Microchip Technology Inc. Description Branch unconditionally Computed branch Branch if Carry (no Borrow) Branch if greater than or equal ...

  • Page 42

    ... Multiply Acc Square to Acc -(Multiply Wn by Wm) to Acc Multiply and subtract from Acc Negate Acc Store Acc Store rounded Acc Arithmetic shift Acc by Slit6 Arithmetic shift Acc by (Wn) Subtract accumulators Preliminary Words Cycles Words Cycles Words Cycles © 2005 Microchip Technology Inc. ...

  • Page 43

    ... In-Circuit Debugger) MPLAB PM3 (see Section 10.7 MPLAB PM3 Universal Device Programmer) Legend: TBD = To Be Determined © 2005 Microchip Technology Inc. Description Integrated Development Environment Assembler (included in MPLAB IDE) Software Simulator (Included in MPLAB IDE) Visual Device Initializer for dsPIC33F (included in MPLAB IDE) ...

  • Page 44

    ... MPLAB ICD full-featured emulator with minimal retraining. Preliminary ® Set break/trace points with a click of the mouse Simply move your mouse over a variable to view or modify Fully customizable watch windows to view and modify registers and memory locations © 2005 Microchip Technology Inc. ...

  • Page 45

    ... UART • 12-Bit ADC • I/O Ports • 10-Bit ADC • Program Flash © 2005 Microchip Technology Inc. 10.4 MPLAB Visual Device Initializer The MPLAB Visual Device Initializer (VDI) simplifies the task of configuring the dsPIC33F. MPLAB VDI software allows you to configure the entire processor graphically (see Figure 10-2). And when you’ ...

  • Page 46

    ... MPLAB C30 C Compiler/Linker/ Librarian The Microchip Technology MPLAB C30 C Compiler provides ‘C’ language support for the dsPIC33F family. This C compiler is a fully ANSI-compliant product with standard libraries highly optimized for the dsPIC33F family and takes advantage of many dsPIC33F architecture-specific features to help you generate very efficient software code ...

  • Page 47

    ... It also includes a Secure Digital/Multimedia Card slot for easy and secure data storage and transfer. © 2005 Microchip Technology Inc. The MPLAB PM3 programmer is designed with 40 programmable socket pins and therefore, each socket module can be configured to support many different devices ...

  • Page 48

    ... Part # SW300020 SW300021 SW300022 SW300023 SW300001 SW300024 SW300002 SW300003-5K SW300003-25K SW300003-100K SW300003-EVAL SW300010-5K SW300010-25K SW300010-100K SW300010-EVAL SW300040-5K SW300040-25K SW300040-100K SW300040-EVAL SW300060-5K SW300060-25K SW300060-100K SW300060-EVAL SW300050-5K SW300050-25K SW300050-100K SW300055-5K SW300055-25K SW300055-100K SW300055-EVAL SW300070-5K SW300070-25K SW300070-100K SW300070-EVAL © 2005 Microchip Technology Inc. ...

  • Page 49

    ... Root and Power Functions Trigonometric and Hyperbolic Functions Logarithmic and Exponential Functions Rounding Functions Absolute Value Functions Modular Arithmetic Functions Comparison and Conversions © 2005 Microchip Technology Inc. TABLE 11-2: MEMORY USAGE AND PERFORMANCE Memory Usage (bytes) Code size Data size ...

  • Page 50

    ... Support for Program Space Visibility • Complete function profile information including register usage, cycle count and function size information • Electronic documentation is included to help you comprehend and use the library functions Preliminary © 2005 Microchip Technology Inc. All DSP routines are ...

  • Page 51

    ... Tool Functions • File Import/Export interoperable with MPLAB IDE • Digital Filtering Options support Filters generated by dsPIC DSC Filter Design • ASM30 Assembler File Option to export Data Tables into dsPIC33F RAM © 2005 Microchip Technology Inc. Number of (1) Conditions Cycles ...

  • Page 52

    ... MPLAB Integrated Development Environment (IDE). System analysis of the filter transfer function is supported with multiple generated graphs, such as magnitude, phase, group delay, log magnitude, impulse response and pole/zero locations. FIGURE 11-2: 3-dimensional Preliminary DIGITAL FILTER DESIGN TOOL INTERFACE © 2005 Microchip Technology Inc. ...

  • Page 53

    ... Transformation Method • Reports show design details, such as all transformations from normalized low-pass filter to desired filter © 2005 Microchip Technology Inc. Code Generation Features • Generated files are compliant with the Microchip dsPIC33F C30 C Compiler, Assembler and Linker • Choice of placement of coefficients in Program Space or Data Space • ...

  • Page 54

    ... RESOURCE REQUIREMENTS • Sampling Interface: Si-3000 Audio Codec operating at 12.0 kHz • System Operating Frequency: 12.288, 18.432 or 24.576 MHz • Computational Power: 8 MIPS • Program Flash Memory 1.5 KB for each library word • RAM: < 3.0 KB Preliminary © 2005 Microchip Technology Inc. ...

  • Page 55

    ... KB 0.5 KB Note: The user application might require an additional 1 KB-1.5 KB for data buffering (application-dependent). © 2005 Microchip Technology Inc. 11.10 Acoustic Echo Cancellation Library The Acoustic Echo Cancellation (AEC) Library provides a function to eliminate echo generated in the acoustic path between a speaker and a microphone. ...

  • Page 56

    ... Optimized for speed, code size and RAM usage - RAM usage below 100 bytes • Library functions extensively tested for adherence to applicable standards • “dsPIC30F Embedded Encryption Libraries User’s Guide” • Several examples of use are provided for each library function Preliminary © 2005 Microchip Technology Inc. ...

  • Page 57

    ... External Flash memory allows you to store many minutes of speech (1 minute of speech requires 60 KB) and it is supported through a general purpose I/O port. © 2005 Microchip Technology Inc. Key features of the Speech Encoding/Decoding Library include: • PESQ-based Mean Opinion Score: 3.7-4.2 (out of 5.0) • ...

  • Page 58

    ... Besides providing development tools and application libraries for dsPIC33F products, Microchip also partners with key third party tool manufacturers to develop quality hardware and software tools in support of the dsPIC33F product family. Details of various third party development tools will be provided shortly. DS70155C-page 56 Preliminary © 2005 Microchip Technology Inc. ...

  • Page 59

    ... Section 13.3 DB9M-DB9M Null Modem Adapter and can be used for Plug-in Modules) library evaluation. © 2005 Microchip Technology Inc. MPLAB In-Circuit Debugger (ICD 2) tool for cost- effective debugging and programming of the dsPIC33F devices. These two boards are shown in Table 13-1. ...

  • Page 60

    ... RS-232 connection with firmware and driver support • LED bank for general indication • Serial EEPROM • alphanumeric LCD • Temperature sensor • Terminal interface program and menu programs FIGURE 13-2: EXPLORER 16 DEVELOPMENT BOARD Preliminary © 2005 Microchip Technology Inc. ...

  • Page 61

    ... TQFP package types for General Purpose and Motor Control Family device samples. The use of plug-in samples is considered interim development board mechanization. © 2005 Microchip Technology Inc. 13.4 Acoustic Accessory Kit The Acoustic Accessory Kit includes the following ...

  • Page 62

    ... Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. ST PORTA is a bidirectional I/O port PORTB is a bidirectional I/O port. Preliminary Description © 2005 Microchip Technology Inc. ...

  • Page 63

    ... REF REF Legend: CMOS = CMOS compatible input or output; Analog = Analog input ST = Schmitt Trigger input with CMOS levels Output Input Power © 2005 Microchip Technology Inc. Type ST PORTC is a bidirectional I/O port PORTD is a bidirectional I/O port. ST PORTE is a bidirectional I/O port. ...

  • Page 64

    ... Prototype samples are intended for dsPIC33F early adopters and are based on early revision silicon. Devices are marked with “PS” suffix. Major differences are noted in this data sheet. For additional information, please refer to the “dsPIC33F Data Sheet” . DS70155C-page 62 RAM (1) ( Preliminary Packages © 2005 Microchip Technology Inc. ...

  • Page 65

    ... SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 REF *Device is marked with ‘PS’ designator. © 2005 Microchip Technology Inc dsPIC33FJ128GP706 Preliminary dsPIC33F EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC2/OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 ...

  • Page 66

    ... AN20/INT1/RA12 13 AN21/INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 *Device is marked with ‘PS’ designator. DS70155C-page 64 dsPIC33FJ128GP708* Preliminary 60 EMUC1/SOSCO/T1CK/CN0/RC14 59 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 58 57 IC4/RD11 IC3/RD10 56 IC2/RD9 55 IC1/RD8 54 SDA2/INT4/RA15 53 SCL2/INT3/RA14 OSC2/CLKO/RC15 50 OSC1/CLKIN/RC12 SCL1/RG2 47 SDA1/RG3 46 EMUC3/SCK1/INT0/RF6 45 SDI1/RF7 44 SDO1/RF8 43 U1RX/RF2 42 EMUD3/U1TX/RF3 41 © 2005 Microchip Technology Inc. ...

  • Page 67

    ... SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 AN5/CN7/RB5 20 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/LVDIN/CN4/RB2 23 PGC/EMUC/AN1/CN3/RB1 24 PGD/EMUD/AN0/CN2/RB0 25 *Device is marked with ‘PS’ designator. © 2005 Microchip Technology Inc. dsPIC33FJ256GP710* Preliminary dsPIC33F EMUC1/SOSCO/T1CK/CN0/RC14 74 EMUD1/SOSCI/CN1/RC13 73 72 EMUC2/OC1/RD0 IC4/RD11 71 IC3/RD10 70 IC2/RD9 69 IC1/RD8 68 INT4/RA15 67 INT3/RA14 OSC2/CLKO/RC15 64 OSC1/CLKIN/RC12 RA5 ...

  • Page 68

    ... SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF DS70155C-page dsPIC33FJ64GP206 41 40 dsPIC33FJ128GP206 Preliminary PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 © 2005 Microchip Technology Inc. ...

  • Page 69

    ... AN16/T2CK/T7CK/RC1 2 AN17/T3CK/T6CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF © 2005 Microchip Technology Inc dsPIC33FJ64GP306 41 dsPIC33FJ128GP306 Preliminary dsPIC33F PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 ...

  • Page 70

    ... AN16/T2CK/T7CK/RC1 2 AN17/T3CK/T6CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF DS70155C-page dsPIC33FJ256GP506 Preliminary PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 © 2005 Microchip Technology Inc. ...

  • Page 71

    ... AN16/T2CK/T7CK/RC1 2 AN17/T3CK/T6CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF © 2005 Microchip Technology Inc dsPIC33FJ64GP706 41 dsPIC33FJ128GP706 Preliminary dsPIC33F PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 ...

  • Page 72

    ... SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 TMS/AN20/INT1/RE8 13 TDO/AN21/INT2/RE9 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC3/EMUC3/AN1/CN3/RB1 19 PGD3/EMUD3/AN0/CN2/RB0 20 DS70155C-page dsPIC33FJ64GP708 51 50 dsPIC33FJ128GP708 Preliminary PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 SDA2/INT4/RA15 SCL2/INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 © 2005 Microchip Technology Inc. ...

  • Page 73

    ... AN17/T3CK/T6CK/RC2 7 AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RE8 18 AN21/INT2/RE9 19 AN5/CN7/RB5 20 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/LVDIN/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 © 2005 Microchip Technology Inc. dsPIC33FJ64GP310 dsPIC33FJ128GP310 Preliminary dsPIC33F PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 72 OC1/RD0 71 IC4/RD11 IC3/RD10 70 69 IC2/RD9 68 IC1/RD8 INT4/RA15 67 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 TDO/RA5 TDI/RA4 60 SDA2/RA3 ...

  • Page 74

    ... AN4/CN6/RB4 21 22 AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 25 PGD3/EMUD3/AN0/CN2/RB0 DS70155C-page 72 dsPIC33FJ256GP510 Preliminary PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 72 OC1/RD0 71 IC4/RD11 IC3/RD10 70 IC2/RD9 69 68 IC1/RD8 67 INT4/RA15 66 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 TDO/RA5 60 TDI/RA4 SDA2/RA3 59 58 SCL2/RA2 57 SCL1/RG2 SDA1/RG3 56 SCK1/INT0/RF6 55 54 SDI1/RF7 SDO1/RF8 53 52 U1RX/RF2 51 U1TX/RF3 © 2005 Microchip Technology Inc. ...

  • Page 75

    ... AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RE8 18 AN21/INT2/RE9 19 AN5/CN7/RB5 20 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/LVDIN/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 © 2005 Microchip Technology Inc. dsPIC33FJ64GP710 dsPIC33FJ128GP710 dsPIC33FJ256GP710 Preliminary dsPIC33F PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 73 72 OC1/RD0 71 IC4/RD11 70 IC3/RD10 IC2/RD9 69 68 IC1/RD8 67 INT4/RA15 66 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 TDO/RA5 TDI/RA4 ...

  • Page 76

    ... External interrupt 2. External interrupt 3. External interrupt 4. PWM Fault A input. PWM Fault B input. PWM 1 low output. PWM 1 high output. PWM 2 low output. PWM 2 high output. PWM 3 low output. PWM 3 high output. PWM 4 low output. PWM 4 high output. Preliminary © 2005 Microchip Technology Inc. ...

  • Page 77

    ... ST Legend: CMOS = CMOS compatible input or output; Analog = Analog input ST = Schmitt Trigger input with CMOS levels Output Input Power © 2005 Microchip Technology Inc. Description Master Clear (Reset) input or programming voltage input. This pin is an active-low Reset to the device. Compare Fault A input (for Compare Channels and 4). ...

  • Page 78

    ... UART2 transmit. Positive supply for peripheral logic and I/O pins. CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input Preliminary Packages © 2005 Microchip Technology Inc. ...

  • Page 79

    ... SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/QEB/IC8/CN7/RB5 11 AN4/QEA/IC7/CN6/RB4 12 AN3/INDX/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 REF *Device is marked with ‘PS’ designator. © 2005 Microchip Technology Inc dsPIC33FJ128MC706 Preliminary dsPIC33F EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC2/OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/FLTB/INT2/RD9 IC1/FLTA/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 ...

  • Page 80

    ... AN5/QEB/CN7/RB5 15 AN4/QEA/CN6/RB4 16 AN3/INDX/CN5/RB3 17 18 AN2/SS1/LVDIN/CN4/RB2 PGC/EMUC/AN1/CN3/RB1 19 20 PGD/EMUD/AN0/CN2/RB0 *Device is marked with ‘PS’ designator. DS70155C-page 78 dsPIC33FJ128MC708* Preliminary 60 EMUC1/SOSCO/T1CK/CN0/RC14 59 EMUD1/SOSCI/CN1/RC13 58 EMUC2/OC1/RD0 57 IC4/RD11 56 IC3/RD10 55 IC2/RD9 54 IC1/RD8 53 SDA2/INT4/RA15 52 SCL2/INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 SCL1/RG2 46 SDA1/RG3 45 EMUC3/SCK1/INT0/RF6 44 SDI1/RF7 SDO1/RF8 43 42 U1RX/RF2 41 EMUD3/U1TX/RF3 © 2005 Microchip Technology Inc. ...

  • Page 81

    ... SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 RA0 17 AN20/FLTA/INT1/RA12 18 AN21/FLTB/INT2/RA13 19 AN5/QEB/CN7/RB5 20 AN4/QEA/CN6/RB4 21 AN3/INDX/CN5/RB3 22 AN2/SS1/LVDIN/CN4/RB2 23 PGC/EMUC/AN1/CN3/RB1 24 PGD/EMUD/AN0/CN2/RB0 25 *Device is marked with ‘PS’ designator. © 2005 Microchip Technology Inc. dsPIC33FJ256MC710* Preliminary dsPIC33F EMUC1/SOSCO/T1CK/CN0/RC14 74 73 EMUD1/SOSCI/CN1/RC13 72 EMUC2/OC1/RD0 71 IC4/RD11 70 IC3/RD10 69 IC2/RD9 68 IC1/RD8 INT4/RA15 67 66 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 ...

  • Page 82

    ... PWM4L/RE6 2 PWM4H/RE7 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/QEB/IC8/CN7/RB5 11 AN4/QEA/IC7/CN6/RB4 12 AN3/INDX/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF DS70155C-page dsPIC33FJ64MC506 Preliminary PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/FLTB/INT2/RD9 IC1/FLTA/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 © 2005 Microchip Technology Inc. ...

  • Page 83

    ... PWM4L/RE6 2 PWM4H/RE7 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 8 SS2/T5CK/CN11/RG9 AN5/QEB/IC8/CN7/RB5 11 AN4/QEA/IC7/CN6/RB4 12 13 AN3/INDX/CN5/RB3 14 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF © 2005 Microchip Technology Inc dsPIC33FJ128MC506 41 dsPIC33FJ64MC506 40 dsPIC33FJ128MC706 Preliminary dsPIC33F PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/FLTB/INT2/RD9 IC1/FLTA/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 ...

  • Page 84

    ... SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 TMS/FLTA/INT1/RE8 13 TDO/FLTB/INT2/RE9 14 AN5/QEB/CN7/RB5 15 AN4/QEA/CN6/RB4 16 AN3/INDX/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC3/EMUC3/AN1/CN3/RB1 19 20 PGD3/EMUD3/AN0/CN2/RB0 DS70155C-page 82 dsPIC33FJ64MC508 Preliminary 60 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 59 PGD2/EMUD2/SOSCI/CN1/RC13 58 OC1/RD0 57 IC4/RD11 56 IC3/RD10 55 IC2/RD9 IC1/RD8 54 53 INT4/RA15 52 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 SCL1/RG2 46 SDA1/RG3 45 SCK1/INT0/RF6 SDI1/RF7 44 SDO1/RF8 43 42 U1RX/RF2 41 U1TX/RF3 © 2005 Microchip Technology Inc. ...

  • Page 85

    ... AN16/T2CK/T7CK/RC1 4 AN17/T3CK/T6CK/RC2 5 SCK2/CN8/RG6 6 7 SDI2/CN9/RG7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 TMS/FLTA/INT1/RE8 13 TDO/FLTB/INT2/RE9 14 AN5/QEB/CN7/RB5 15 AN4/QEA/CN6/RB4 16 17 AN3/INDX/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 18 PGC3/EMUC3/AN1/CN3/RB1 19 20 PGD3/EMUD3/AN0/CN2/RB0 © 2005 Microchip Technology Inc. dsPIC33FJ128MC708 Preliminary dsPIC33F 60 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 59 PGD2/EMUD2/SOSCI/CN1/RC13 58 OC1/RD0 57 IC4/RD11 IC3/RD10 56 55 IC2/RD9 54 IC1/RD8 53 SDA2/INT4/RA15 SCL2/INT3/RA14 OSC2/CLKO/RC15 50 49 OSC1/CLKIN/RC12 SCL1/RG2 SDA1/RG3 46 ...

  • Page 86

    ... AN4/QEA/CN6/RB4 21 AN3/INDX/CN5/RB3 22 AN2/SS1/LVDIN/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 DS70155C-page 84 dsPIC33FJ64MC510 Preliminary PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 72 OC1/RD0 IC4/RD11 71 70 IC3/RD10 IC2/RD9 69 68 IC1/RD8 67 INT4/RA15 66 INT3/RA14 OSC2/CLKO/RC15 64 63 OSC1/CLKIN/RC12 TDO/RA5 TDI/RA4 60 RA3 59 RA2 58 57 SCL1/RG2 56 SDA1/RG3 SCK1/INT0/RF6 55 54 SDI1/RF7 SDO1/RF8 53 U1RX/RF2 52 51 U1TX/RF3 © 2005 Microchip Technology Inc. ...

  • Page 87

    ... AN17/T3CK/T6CK/RC2 7 AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/FLTA/INT1/RE8 18 AN21/FLTB/INT2/RE9 19 AN5/QEB/CN7/RB5 20 AN4/QEA/CN6/RB4 21 AN3/INDX/CN5/RB3 22 AN2/SS1/LVDIN/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 25 PGD3/EMUD3/AN0/CN2/RB0 © 2005 Microchip Technology Inc. dsPIC33FJ128MC510 dsPIC33FJ256MC510 Preliminary dsPIC33F PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 72 OC1/RD0 71 IC4/RD11 70 IC3/RD10 69 IC2/RD9 68 IC1/RD8 67 INT4/RA15 66 INT3/RA14 OSC2/CLKO/RC15 64 63 OSC1/CLKIN/RC12 TDO/RA5 60 TDI/RA4 ...

  • Page 88

    ... AN5/QEB/CN7/RB5 20 AN4/QEA/CN6/RB4 21 AN3/INDX/CN5/RB3 22 AN2/SS1/LVDIN/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 DS70155C-page 86 dsPIC33FJ64MC710 dsPIC33FJ128MC710 dsPIC33FJ256MC710 Preliminary PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 72 71 IC4/RD11 70 IC3/RD10 IC2/RD9 69 IC1/RD8 68 INT4/RA15 67 66 INT3/RA14 OSC2/CLKO/RC15 64 OSC1/CLKIN/RC12 TDO/RA5 60 TDI/RA4 SDA2/RA3 59 SCL2/RA2 58 57 SCL1/RG2 56 SDA1/RG3 55 SCK1/INT0/RF6 54 SDI1/RF7 53 SDO1/RF8 52 U1RX/RF2 51 U1TX/RF3 © 2005 Microchip Technology Inc. ...

  • Page 89

    ... NOTES: © 2005 Microchip Technology Inc. Preliminary dsPIC33F DS70155C-page 87 ...

  • Page 90

    ... Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Preliminary © 2005 Microchip Technology Inc. EUROPE Austria - Weis Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...