PIC18F2550-I/SP Microchip Technology, PIC18F2550-I/SP Datasheet - Page 228

• Manufacturer Part Number: PIC18F2550-I/SP
• Description: IC PIC MCU FLASH 16KX16 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2550-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: SPI, I2C, EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163025, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRDDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2455/2550/4455/4550
19.4.6
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware if the TRIS bits
are set.
Master mode operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I
set or the bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I
Stop bit conditions.
Once Master mode is enabled, the user has six
options:
1.
2.
3.
4.
5.
6.
FIGURE 19-18:
DS39632E-page 226
Assert a Start condition on SDA and SCL.
Assert a Repeated Start condition on SDA and
SCL.
Write
transmission of data/address.
Configure the I
Generate an Acknowledge condition at the end
of a received byte of data.
Generate a Stop condition on SDA and SCL.
SDA
SCL
MASTER MODE
to
2
C bus operations based on Start and
2
C bus may be taken when the P bit is
the
2
C port to receive data.
SSPBUF
MSSP BLOCK DIAGRAM (I
SDA In
Bus Collision
SCL In
register
Read
initiating
MSb
Write Collision Detect
Start bit, Stop bit,
End of XMIT/RCV
State Counter for
Clock Arbitration
Acknowledge
Start bit Detect
Stop bit Detect
SSPBUF
Generate
SSPSR
2
C™ MASTER MODE)
LSb
Write
The following events will cause the MSSP Interrupt
Flag bit, SSPIF, to be set (and MSSP interrupt, if
enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
Clock
Note:
Data Bus
Shift
Internal
Set/Reset S, P, WCOL (SSPSTAT, SSPCON1);
set SSPIF, BCLIF;
reset ACKSTAT, PEN (SSPCON2)
The MSSP module, when configured in
I
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
2
C Master mode, does not allow queueing
© 2009 Microchip Technology Inc.
SSPM3:SSPM0
SSPADD<6:0>
Generator
Baud
Rate