ATMEGA644V-10AU Atmel, ATMEGA644V-10AU Datasheet - Page 153

• Manufacturer Part Number: ATMEGA644V-10AU
• Description: IC AVR MCU FLASH 64K 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA644V-10AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 44TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 10 MHz
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.11.9
2593N–AVR–07/10
GTCCR – General Timer/Counter Control Register
rupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In
PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.
Bit
0x23 (0x43)
Read/Write
Initial Value
• Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the
• Bit 1 – PSRASY: Prescaler Reset Timer/Counter2
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared
immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous
mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by
hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/Counter Syn-
chronization Mode” on page 136 for a description of the Timer/Counter Synchronization mode.
• Bit 0– PSRSYNC :Prescaler Reset When this bit is one, Timer/Counter1 and Timer/Counter0
Timer/Counter Synchronization mode. In this mode, the value that is written to the PSRASY
and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals
asserted. This ensures that the corresponding Timer/Counters are halted and can be
configured to the same value without the risk of one of them advancing during configuration.
When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared by
hardware, and the Timer/Counters start counting simultaneously.
prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the
TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a
reset of this prescaler will affect both timers.
TSM
R/W
7
0
6
–
R
0
R
5
–
0
R
4
–
0
R
3
–
0
R
2
–
0
PSRASY
R/W
1
0
ATmega644
PSRSYNC
R/W
0
0
GTCCR
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