PIC16LC73A-04/SO Microchip Technology, PIC16LC73A-04/SO Datasheet - Page 45

• Manufacturer Part Number: PIC16LC73A-04/SO
• Description: IC MCU OTP 4KX14 A/D PWM 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC73A-04/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.2
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISB. Setting a bit
in the TRISB register puts the corresponding output
driver in a hi-impedance input mode. Clearing a bit in
the TRISB register puts the contents of the output latch
on the selected pin(s).
EXAMPLE 5-2:
BCF
CLRF
BSF
MOVLW
MOVWF
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (OPTION<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
FIGURE 5-3:
Data bus
WR TRIS
WR Port
RB0/INT
RBPU
1997 Microchip Technology Inc.
Note 1: I/O pins have diode protection to V
(2)
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
STATUS, RP0
PORTB
STATUS, RP0
0xCF
TRISB
PORTB and TRISB Registers
and clear the RBPU bit (OPTION<7>).
Applicable Devices
72 73 73A 74 74A 76 77
BLOCK DIAGRAM OF
RB3:RB0 PINS
RD TRIS
RD Port
Data Latch
TRIS Latch
INITIALIZING PORTB
D
D
CK
CK
Schmitt Trigger
Buffer
;
; Initialize PORTB by
; clearing output
; data latches
; Select Bank 1
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Q
Q
DD
Q
and V
EN
TTL
Input
Buffer
D
SS
.
V
P
RD Port
DD
weak
pull-up
I/O
pin
(1)
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e. any RB7:RB4 pin con-
figured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
rupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with soft-
ware configurable pull-ups on these four pins allow
easy interface to a keypad and make it possible for
wake-up on key-depression. Refer to the Embedded
Control Handbook, "Implementing Wake-Up on Key
Stroke" (AN552).
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
Note:
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
For the PIC16C73/74, if a change on the
I/O pin should occur when the read opera-
tion is being executed (start of the Q2
cycle), then interrupt flag bit RBIF may not
get set.
PIC16C7X
DS30390E-page 45