PIC18F4585-I/ML Microchip Technology, PIC18F4585-I/ML Datasheet - Page 6

• Manufacturer Part Number: PIC18F4585-I/ML
• Description: IC MCU FLASH 24KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4585-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Core: PIC
• Processor Series: PIC18F
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Data Ram Size: 3.25 KB
• On-chip Adc: 11 bit
• Number Of Programmable I/os: 44
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 4.2 V to 5.5 V
• Mounting Style: SMD/SMT
• Height: 0.88 mm
• Interface Type: I2C, SPI, EUSART
• Length: 8 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.2 V
• Width: 8 mm
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNI3-DB18F4680 - BOARD DAUGHTER ICEPIC3444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2585/2680/4585/4680
24. Module: Interrupts
EXAMPLE 3:
DS80283E-page 6
ISR @ 0x0008
Foo:
CALL
POP
:
:
RETFIE
If an interrupt occurs during a two-cycle instruction
that modifies the STATUS, BSR or WREG register,
the unmodified value of the register will be saved
to the corresponding Fast Return (Shadow)
register. Upon a fast return from the interrupt, the
unmodified value will be restored to the STATUS,
BSR or WREG register.
For example, if a high priority interrupt occurs
during the instruction “MOVFF TEMP, WREG”, the
MOVFF instruction will be completed and WREG
will be loaded with the value of TEMP before
branching to ISR. However, the previous value of
WREG will be saved to the Fast Return register
during ISR branching. Upon return from the
interrupt with a fast return, the previous value of
WREG in the Fast Return register will be written to
WREG. This results in WREG containing the value
it had before execution of MOVFF TEMP, WREG.
Affected instructions are:
MOVFF Fs, Fd
where Fd is WREG, BSR or STATUS;
MOVSF Zs, Fd
where Fd is WREG, BSR or STATUS; and
MOVSS [Zs], [Zd]
where the destination is WREG, BSR or STATUS.
2. C Language Programming: The exact work
around depends on the compiler in use. Please
refer to your C compiler documentation for
details.
If using the Microchip MPLAB
define both high and low priority interrupt
handler functions as “low priority” by using the
pragma interruptlow directive. This direc-
tive instructs the compiler to not use the
RETFIE FAST instruction. If the proper high
priority interrupt bit is set in the IPRx register,
then the interrupt is treated as high priority in
spite of the pragma interruptlow directive.
Foo, FAST
FAST
; store current value of WREG, BSR, STATUS for a second time
; clears return address of Foo call
; insert high priority ISR code here
®
C18 C Compiler,
Work around
1. Assembly Language Programming:
a) If any two-cycle instruction is used to mod-
b) As another alternative, the following work
The code segment, shown in Example 4 on the
following page, demonstrates the work around
using the C18 compiler.
ify the WREG, BSR or STATUS register,
do not use the RETFIE FAST instruction
to return from the interrupt. Instead, save/
restore WREG, BSR and STATUS via
software per Example 8-1 in the Device
Data Sheet. Alternatively, in the case of
MOVFF, use the MOVF instruction to write to
WREG instead.
For example, use:
MOVF
MOVWF BSR
instead of
around shown in Example 3 can be used.
This example overwrites the Fast Return
register by making a dummy call to Foo
with the fast option in the high priority
service routine.
TEMP, W
MOVFF TEMP, BSR.
© 2007 Microchip Technology Inc.