PIC18F4685-I/ML Microchip Technology, PIC18F4685-I/ML Datasheet - Page 342

• Manufacturer Part Number: PIC18F4685-I/ML
• Description: IC PIC MCU FLASH 48KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4685-I/ML

• Core Size: 8-Bit
• Program Memory Size: 96KB (48K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3328Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNI3-DB18F4680 - BOARD DAUGHTER ICEPIC3444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / Rohs Status: Details

COMSTAT. In Mode 1 and 2, there are two interrupt
PIC18F2682/2685/4682/4685
FIGURE 23-8:
23.15 CAN Interrupts
The module has several sources of interrupts. Each of
these interrupts can be individually enabled or
disabled. The PIR3 register contains interrupt flags.
The PIE3 register contains the enables for the 8 main
interrupts. A special set of read-only bits in the
CANSTAT register, the ICODE bits, can be used in
combination with a jump table for efficient handling of
interrupts.
All interrupts have one source, with the exception of the
error interrupt and buffer interrupts in Mode 1 and 2. Any
of the error interrupt sources can set the error interrupt
flag. The source of the error interrupt can be determined
by
enable/disable and flag bits – one for all transmit buffers
and the other for all receive buffers.
DS39761C-page 342
reading
the
Communication
ERROR MODES STATE DIAGRAM
RXERRCNT < 127 or
TXERRCNT < 127
Passive
Error
Status
-
register,
TXERRCNT > 255
RXERRCNT > 127 or
TXERRCNT > 127
Active
Error
The interrupts can be broken up into two categories:
receive and transmit interrupts.
The receive related interrupts are:
• Receive Interrupts
• Wake-up Interrupt
• Receiver Overrun Interrupt
• Receiver Warning Interrupt
• Receiver Error-Passive Interrupt
The transmit related interrupts are:
• Transmit Interrupts
• Transmitter Warning Interrupt
• Transmitter Error-Passive Interrupt
• Bus-Off Interrupt
-
Bus-
Off
Reset
128 occurrences of
11 consecutive
“recessive” bits
© 2009 Microchip Technology Inc.