DSPIC30F6012A-30I/PT Microchip Technology, DSPIC30F6012A-30I/PT Datasheet
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... Microchip Technology Inc. High-Performance, 16-bit Digital Signal Controllers Data Sheet DS70143E ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... All DSP instructions are single cycle: - Multiply-Accumulate (MAC) operation • Single-cycle ±16 shift © 2011 Microchip Technology Inc. dsPIC30F6011A/6012A/6013A/6014A Peripheral Features: • High-current sink/source I/O pins: 25 mA/25 mA • Five 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules • ...
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... Low-power, high-speed Flash technology • Wide operating voltage range (2.5V to 5.5V) • Industrial and Extended temperature ranges • Low power consumption dsPIC30F6011A/6012A/6013A/6014A Controller Families Program Memory Device Pins Bytes Instructions dsPIC30F6011A 64 132K 44K dsPIC30F6012A 64 144K 48K dsPIC30F6013A 80 132K 44K dsPIC30F6014A 80 144K 48K DS70143E-page 4 ...
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... TQFP RG15 1 T2CK/RC1 2 T3CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 REF © 2011 Microchip Technology Inc. 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/INT2/RD9 42 IC1/INT1/RD8 dsPIC30F6011A 40 OSC2/CLKO/RC15 39 OSC1/CLKI SCL/RG2 36 SDA/RG3 35 EMUC3/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 EMUD3/U1TX/SDO1/RF3 DS70143E-page 5 ...
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... TQFP COFS/RG15 1 T2CK/RC1 2 T3CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 REF DS70143E-page 6 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/INT2/RD9 42 IC1/INT1/RD8 dsPIC30F6012A 40 OSC2/CLKO/RC15 39 OSC1/CLKI SCL/RG2 36 SDA/RG3 35 EMUC3/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 EMUD3/U1TX/SDO1/RF3 © 2011 Microchip Technology Inc. ...
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... T2CK/RC1 2 3 T3CK/RC2 4 T4CK/RC3 T5CK/RC4 5 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 INT1/RA12 13 INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 © 2011 Microchip Technology Inc dsPIC30F6013A EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI V DD SCL/RG2 SDA/RG3 EMUC3/SCK1/INT0/RF6 SDI1/RF7 ...
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... T5CK/RC4 5 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 INT1/RA12 13 INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 DS70143E-page dsPIC30F6014A EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI V DD SCL/RG2 SDA/RG3 EMUC3/SCK1/INT0/RF6 SDI1/RF7 EMUD3/SDO1/RF8 U1RX/RF2 U1TX/RF3 © 2011 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com © 2011 Microchip Technology Inc. to receive the most current information on all of our products. DS70143E-page 9 ...
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... NOTES: DS70143E-page 10 © 2011 Microchip Technology Inc. ...
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... Controller (DSC) devices. The dsPIC30F devices contain extensive Digital Signal Processor (DSP) func- tionality within a high-performance microcontroller (MCU) architecture. Figure 1-2 show device block dsPIC30F6011A/6012A and dsPIC30F6013A/6014A, respectively. © 2011 Microchip Technology Inc. Manual” 16-bit Figure 1-1 and diagrams for DS70143E-page 11 ...
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... Generation Start-up Timer POR/BOR Watchdog MCLR Timer Low-Voltage Detect CAN1, 12-bit ADC CAN2 Timers Note 1: CSDI, CSDO, CSCK, and COFS are codec functions on dsPIC30F6012A only. DS70143E-page 12 X Data Bus Data Latch Data Latch Y Data X Data 16 RAM RAM 16 Address Address Latch Latch 16 ...
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... Watchdog MCLR Timer Low-Voltage Detect CAN1, Capture 12-bit ADC CAN2 Timers Note 1: CSDI, CSDO, CSCK, and COFS are codec functions on dsPIC30F6014A only © 2011 Microchip Technology Inc. X Data Bus Data Latch Data Latch Y Data X Data 16 RAM RAM 16 Address Address Latch Latch 16 ...
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... Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input DS70143E-page 14 Description Analog = Analog input O = Output P = Power © 2011 Microchip Technology Inc. ...
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... Analog Analog Voltage Reference (High) input. REF Analog Analog Voltage Reference (Low) input. REF Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2011 Microchip Technology Inc. Description 2 C™ Analog = Analog input O = Output P = Power DS70143E-page 15 ...
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... NOTES: DS70143E-page 16 © 2011 Microchip Technology Inc. ...
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... Each data word consists of 2 bytes, and most instructions can address data either as words or bytes. © 2011 Microchip Technology Inc. There are two methods of accessing data stored in program memory: • The upper 32 Kbytes of data space memory can ...
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... DSP Adder/Subtracter status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) status bit. 2.2.3 PROGRAM COUNTER The Program Counter is 23-bits wide; bit 0 is always clear. Therefore, the PC can address instruction words. DSC devices contain a software stack. Figure 2-1 for SR layout. © 2011 Microchip Technology Inc. ...
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... AD39 DSP ACCA Accumulators ACCB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2011 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 AD31 PC0 0 ...
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... TABLE 2-1: DSP INSTRUCTIONS SUMMARY Algebraic Instruction Operation CLR – – y) EDAC MAC MAC No change in A MOVSAC MPY MPY MPY – – MSC Function © 2011 Microchip Technology Inc. operations, selection 3-3. ACC Write Back Yes No No Yes No Yes Yes ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2011 Microchip Technology Inc. 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill DS70143E-page 21 ...
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... OVBTE) in the INTCON1 register (refer to rupts”) is set. This allows the user to take immediate action, for example, to correct system gain. Section 5.0 “Inter- © 2011 Microchip Technology Inc. ...
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... If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. © 2011 Microchip Technology Inc. 2.4.2.2 Accumulator ‘Write Back’ The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a ...
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... The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is pre- sented to the barrel shifter between bit positions for right shifts, and bit positions for left shifts. © 2011 Microchip Technology Inc. ...
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... Note that the program space address is incremented by two between succes- sive program words in order to provide compatibility with data space addressing. © 2011 Microchip Technology Inc. User program space access is restricted to the lower 4M instruction word address range (0x000000 to 0x7FFFFE) for all accesses other than TBLRD/TBLWT, which use TBLPAG< ...
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... F7FFFE F80000 F8000E F80010 FEFFFE FF0000 FFFFFE PROGRAM SPACE MEMORY MAP FOR dsPIC30F6012A/ 6014A Reset – GOTO Instruction 000000 Reset – Target Address 000002 000004 Vector Tables Interrupt Vector Table 00007E Reserved 000080 000084 Alternate Vector Table ...
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... Program 0 Space Visibility Using 1/0 Table Instruction User/ Configuration Space Select Note: Program space visibility cannot be used to access bits <23:16> word in program memory. © 2011 Microchip Technology Inc. Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> PSVPAG<7:0> bits Program Counter Select 1 EA ...
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... The destination byte will always when byte select = 1. 4. TBLWTH: Table Write High (refer to “Flash Program Memory” Programming TBLRDL.B (Wn<0> TBLRDL.W TBLRDL.B (Wn<0> Section 6.0 for details on Flash Section 6.0 for details on Flash 0 © 2011 Microchip Technology Inc. ...
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... The upper 8 bits should be programmed to force an illegal instruction to maintain machine robustness. Refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157) for details on instruction encoding. © 2011 Microchip Technology Inc. TBLRDH TBLRDH.B (Wn<0> TBLRDH.B (Wn< ...
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... Note 1: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines the page in program space to which the upper half of data space is being mapped). DS70143E-page 30 Program Space 0x0000 (1) PSVPAG 0x02 8 0x8000 23 15 Address Concatenation 15 23 0xFFFF 0x000100 0 0x010000 0x017FFF Data Read © 2011 Microchip Technology Inc. ...
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... The data space memory maps are shown in and Figure 3-9. © 2011 Microchip Technology Inc. 3.2.2 DATA SPACES The X data space is used by all instructions and sup- ports all Addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space ...
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... Optionally Mapped into Program Memory 0xFFFF DS70143E-page 32 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x17FE 0x1800 0x1FFE Y Data RAM (Y) 0x1FFE 0x2000 0x8000 X Data Unimplemented (X) 0xFFFE 8 Kbyte Near Data Space © 2011 Microchip Technology Inc. ...
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... FIGURE 3-8: DATA SPACE MEMORY MAP FOR dsPIC30F6012A/6014A MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 8 Kbyte 0x17FF 0x1801 SRAM Space 0x1FFF 0x27FF 0x2801 0x8001 Optionally Mapped into Program Memory 0xFFFF © 2011 Microchip Technology Inc. LSB 16 bits Address MSB ...
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... For example, the core would recognize that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value for byte operations and for word operations. SFR SPACE UNUSED ® © 2011 Microchip Technology Inc. ...
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... Additionally, the whole of X data space is addressable using MOV instructions, which support memory direct addressing with a 16-bit address field. © 2011 Microchip Technology Inc. 3.2.6 SOFTWARE STACK The dsPIC DSC devices contain a software stack. W15 is used as the Stack Pointer. ...
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... Boot Segment Flash code when enabled. SSRAM (Secure RAM segment for RAM) is accessible only from the Secure Segment Flash code when enabled. See Table 3-3 for an overview of the BSRAM and SSRAM SFRs. DS70143E-page 36 devices © 2011 Microchip Technology Inc. ...
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... Microchip Technology Inc. DS70143E-page 37 ...
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... DS70143E-page 38 © 2011 Microchip Technology Inc. ...
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... Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2011 Microchip Technology Inc. 4.1.1 FILE REGISTER INSTRUCTIONS Most File register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (Near data space) ...
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... The only exception to the usage restrictions is for buf- fers which have a power-of-2 length. As these buffers satisfy the start and end address criteria, they may operate in a Bidirectional mode (i.e., address boundary checks will be performed on both the lower and upper address boundaries). © 2011 Microchip Technology Inc. ...
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... MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2011 Microchip Technology Inc. 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control reg- ister MODCON<15:0> contains enable flags as well as Table 3-3). ...
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... If Bit-Reversed Addressing has already been enabled by setting the BREN (XBREV<15>) bit, then a write to Bit-Reversed the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. N bytes, should not be enabled © 2011 Microchip Technology Inc. ...
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... BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 4096 2048 1024 512 256 128 © 2011 Microchip Technology Inc. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer Bit-Reversed Address ...
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... NOTES: DS70143E-page 44 © 2011 Microchip Technology Inc. ...
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... Interrupt level (ILR<3:0>) bit fields in the INTTREG register. The new interrupt priority level is the priority of the pending interrupt. © 2011 Microchip Technology Inc. • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers. INTCON1 contains the con- trol and status flags for the processor exceptions ...
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... C2 – Combined IRQ for CAN2 39-40 47-48 Reserved 41 49 DCI – Codec Transfer Done 42 50 LVD – Low-Voltage Detect 43-53 51-61 Reserved Lowest Natural Order Priority Note 1: Reserved on dsPIC30F6011A and dsPIC30F6013A because the DCI module is not available on these devices. © 2011 Microchip Technology Inc. (1) ...
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... Microchip Technology Inc. Note that many of these trap conditions can only be detected when they occur. Consequently, the question- able instruction is allowed to complete prior to trap exception processing ...
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... The processor then loads the priority level for this inter- rupt into the STATUS register. This action will disable all lower priority interrupts until the completion of the Interrupt Service Routine. © 2011 Microchip Technology Inc. 0x000000 0x000002 0x000004 0x000014 ...
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... If the AIVT is not required, the program memory allo- cated to the AIVT may be used for other purposes. AIVT is not a protected section and may be freely programmed by the user. © 2011 Microchip Technology Inc. 5.6 Fast Context Saving A context saving option is available using shadow reg- isters ...
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... DS70143E-page 50 © 2011 Microchip Technology Inc. ...
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... NVMADR Addressing Using Table Instruction User/Configuration Space Select © 2011 Microchip Technology Inc. 6.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... NVMKEY register. Refer to DD “Programming Operations” Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. © 2011 Microchip Technology Inc. Section 6.6 for further details. ...
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... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2011 Microchip Technology Inc. 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Set up NVMCON register for multi-word, program Flash, program, and set WREN bit ...
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... NOPs. ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted © 2011 Microchip Technology Inc. ...
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... NOTES: DS70143E-page 56 © 2011 Microchip Technology Inc. ...
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... The write typ- ically requires complete but the write time will vary with voltage and temperature. © 2011 Microchip Technology Inc. A program or erase operation on the data EEPROM does not stop the instruction flow. The user is respon- sible for waiting for the appropriate duration of time before initiating another data EEPROM write/erase operation ...
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... Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence © 2011 Microchip Technology Inc. ...
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... Write cycle will complete in 2 ms. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2011 Microchip Technology Inc. The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared; also, the Power-up Timer prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch, or software malfunction. © 2011 Microchip Technology Inc. ...
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... WR LAT + WR Port Read LAT Read Port © 2011 Microchip Technology Inc. Any bit and its associated data and control registers that are not valid for a particular device will be dis- abled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. ...
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... Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the ) will be OL device specifications. Output Multiplexers 1 Output Enable 0 1 Output Data Input Data I/O Cell I/O Pad © 2011 Microchip Technology Inc. ...
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... Bit 1 Bit 0 Reset State CN1IE CN0IE 0000 0000 0000 0000 CN17IE CN16IE 0000 0000 0000 0000 CN1PUE CN0PUE 0000 0000 0000 0000 0000 0000 0000 0000 © 2011 Microchip Technology Inc. ...
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... TGATE SOSCO/ T1CK LPOSCEN SOSCI © 2011 Microchip Technology Inc. These Operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit Timer1 module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer ...
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... Low power • Real-Time Clock interrupts These Operating modes are determined by setting the appropriate bit(s) in the T1CON Control register. FIGURE 9-2: RECOMMENDED COMPONENTS FOR TIMER1 LP OSCILLATOR RTC C1 32.768 kHz XTAL pF 100K © 2011 Microchip Technology Inc. SOSCI dsPIC30FXXXX SOSCO ...
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... Timer interrupt flag, T1IF, is located in the IFS0 status register in the interrupt controller. Enabling an interrupt is accomplished via the respec- tive timer interrupt enable bit, T1IE. The timer interrupt enable bit is located in the IEC0 Control register in the interrupt controller. © 2011 Microchip Technology Inc. DS70143E-page 69 ...
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... DS70143E-page 70 © 2011 Microchip Technology Inc. ...
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... Interrupt on a 32-bit period register match These Operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2011 Microchip Technology Inc. For 32-bit timer/counter operation, Timer2 is the lsw and Timer3 is the most significant word (msw) of the 32-bit timer. ...
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... Timer configuration bit T32 (T2CON<3>) must be set to ‘ bits are respective to the T2CON register. DS70143E-page TMR3 TMR2 MSB LSB Comparator x 32 PR3 PR2 TGATE (T2CON<6> Gate Sync ’ for a 32-bit timer/counter operation. All control 1 Sync TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2011 Microchip Technology Inc. ...
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... Equal Reset 0 T2IF Event Flag 1 TGATE T2CK FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE T3CK © 2011 Microchip Technology Inc. PR2 Comparator x 16 TMR2 TGATE TON 1 x Gate Sync PR3 Comparator x 16 TMR3 ...
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... In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T3IE (IEC0<7>). © 2011 Microchip Technology Inc. ...
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... T4CK Note: Timer configuration bit T32 (T4CON<3>) must be set to ‘ bits are respective to the T4CON register. © 2011 Microchip Technology Inc. • The Timer4/5 module does not support the ADC event trigger feature • Timer4/5 can not be utilized by other peripheral modules, such as input capture and ...
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... Reset 0 T5IF Event Flag 1 TGATE T5CK Note: In the dsPIC30F6011A and dsPIC30F6012A devices, there is no T5CK pin. Therefore, in this device the following modes should not be used for Timer5: TCS = 1 (16-bit Counter) TCS = 0, TGATE = 1 (Gated Time Accumulation) DS70143E-page 78 PR4 Comparator x 16 TMR4 TGATE ...
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... Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N. © 2011 Microchip Technology Inc. These Operating modes are determined by setting the appropriate bits in the ICxCON register (where x = 1,2,...,N). The dsPIC DSC devices contain capture channels (i ...
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... IFSx status register. Enabling an interrupt is accomplished via the respec- tive capture channel interrupt enable (ICxIE) bit. The capture interrupt enable bit is located in the corresponding IEC control register. © 2011 Microchip Technology Inc. defined as ...
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... TMR3<15:0> Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through N. © 2011 Microchip Technology Inc. The key operational features of the output compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...
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... Fault condition has occurred. This state will be main- tained until both of the following events have occurred: • The external Fault condition has been removed. • The PWM mode has been re-enabled by writing to the appropriate control bits © 2011 Microchip Technology Inc. ...
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... Duty Cycle TMR3 = PR3 T3IF = 1 (Interrupt Flag) OCxR = OCxRS © 2011 Microchip Technology Inc. When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • TMRx is cleared • The OCx pin is set ...
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... IFS0 status register and must be cleared in software. The interrupt is enabled via the respective timer interrupt enable bit (T2IE or T3IE) located in the IEC0 control register. The output compare interrupt flag is never set during the PWM mode of operation. © 2011 Microchip Technology Inc. ...
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... SCL transitions while SPIROV is ‘1’, effectively disabling the module until SPIxBUF is read by user software. © 2011 Microchip Technology Inc. Transmit writes are also double-buffered. The user writes to SPIxBUF. When the master or slave transfer is completed, the contents of the shift register (SPIxSR) are moved to the receive buffer ...
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... Clock Clock Edge Control Select Enable Master Clock SDOx SDIy SDIx SDOy LSb Serial Clock SCKx SCKy Secondary Primary F Prescaler CY Prescaler 1:1 – 1 16, 64 SPI Slave Serial Input Buffer (SPIyBUF) Shift Register (SPIySR) MSb LSb PROCESSOR 2 © 2011 Microchip Technology Inc. ...
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... The transmitter and receiver will stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode. © 2011 Microchip Technology Inc. 14.5 SPI Operation During CPU Idle Mode When the device enters Idle mode, all clock sources remain functional. The SPISIDL bit (SPIxSTAT< ...
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... DS70143E-page 94 © 2011 Microchip Technology Inc. ...
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... Thus, the I C module can operate either as a slave master bus. FIGURE 15-1: PROGRAMMER’S MODEL Bit 15 Bit 15 © 2011 Microchip Technology Inc. 15.1.1 VARIOUS I The following types • slave operation with 7-bit addressing 2 • slave operation with 10-bit addressing 2 • ...
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... LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter F CY Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read © 2011 Microchip Technology Inc. ...
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... SCL high. The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2011 Microchip Technology Inc. 15.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated ...
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... C bus have deasserted SCL. This ensures that a write to the SCLREL bit will not violate the minimum high time requirement for SCL. If the STREN bit is ‘0’, a software write to the SCLREL bit will be disregarded and have no effect on the SCLREL bit. © 2011 Microchip Technology Inc. 2 CRCV ...
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... Generate a Stop condition on SDA and SCL. 2 • Configure the I C port to receive data. • Generate an ACK condition at the end of a received byte of data. © 2011 Microchip Technology Inc. 2 15. Master Operation The master device generates all of the serial clock 2 C Slave Inter- pulses and the Start and Stop conditions ...
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... C OPERATION DURING CPU IDLE MODE 2 For the I C, the I2CSIDL bit selects if the module will stop on Idle or continue on Idle. If I2CSIDL = 0, the module will continue operation on assertion of the Idle mode. If I2CSIDL = 1, the module will stop on Idle bus © 2011 Microchip Technology Inc. ...
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... NOTES: DS70143E-page 102 © 2011 Microchip Technology Inc. ...
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... Internal Data Bus UTXBRK Data UxTX Parity Note © 2011 Microchip Technology Inc. 16.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, odd or no parity options (for 8-bit data) • One or two Stop bits • ...
Page 104
... Receive Buffer Control 8-9 Load RSR to Buffer Receive Shift Register (UxRSR) 16 Divider 16x Baud Clock from Baud Rate Generator Read Read Write UxMODE UxSTA – Generate Flags – Generate Interrupt – Shift Data Characters Control Signals UxRXIF © 2011 Microchip Technology Inc. ...
Page 105
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity and 1 Stop bit (typically represented 1). © 2011 Microchip Technology Inc. 16.3 Transmitting Data 16.3.1 TRANSMITTING IN 8-BIT DATA ...
Page 106
... Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. RECEIVE BUFFER (U RXB) X RECEIVE INTERRUPT RECEIVE BUFFER OVERRUN ERROR (OERR BIT) © 2011 Microchip Technology Inc. ...
Page 107
... FERR bit set. The break character is loaded into the buffer. No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not yet been received. © 2011 Microchip Technology Inc. 16.6 Address Detect Mode Setting the ADDEN bit (UxSTA<5>) enables this spe- cial mode in which a 9th bit (URX8) value of ‘ ...
Page 108
... For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode or whether the module will continue on Idle. If USIDL = 0, the module will continue operation during Idle mode. If USIDL = 1, the module will stop on Idle. © 2011 Microchip Technology Inc. ...
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... Microchip Technology Inc. DS70143E-page 109 ...
Page 110
... NOTES: DS70143E-page 110 © 2011 Microchip Technology Inc. ...
Page 111
... CAN1 and CAN2) for time-stamping and network synchronization • Low-power Sleep and Idle mode © 2011 Microchip Technology Inc. The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine handles all functions for receiving and transmitting messages on the CAN bus ...
Page 112
... Acceptance Filter c RXF3 c Acceptance Filter e RXF4 p t Acceptance Filter RXF5 R M Identifier Data Field Receive RERRCNT Error Counter TERRCNT Transmit Err Pas Error Bus Off Counter Protocol Finite State Machine Bit Timing Bit Timing Logic Generator (1) CiRX © 2011 Microchip Technology Inc. ...
Page 113
... Module Disable mode. The I/O pins will revert to normal I/O function when the module is in the Module Disable mode. © 2011 Microchip Technology Inc. The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2< ...
Page 114
... End of Frame (EOF) field. Reading the RXnIF flag will indicate which receive buffer caused the interrupt. • Wake-up Interrupt: The CAN module has woken up from Disable mode or the device has woken up from Sleep mode. © 2011 Microchip Technology Inc. ...
Page 115
... SOF occurs. When the TXREQ is set, the TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR (CiTXnCON<4>) flag bits are automatically cleared. © 2011 Microchip Technology Inc. Setting the TXREQ bit simply flags a message buffer as enqueued for transmission. When the module detects an available bus, it begins transmitting the message which has been determined to have the highest priority ...
Page 116
... definition, the nominal bit time has a minimum and a maximum the minimum nominal bit time is 1 μsec corresponding to a maximum bit rate of 1 MHz. Phase Phase Segment 1 Segment 2 Sample Point Figure 17-2. . Also, by definition, Q Sync © 2011 Microchip Technology Inc. ...
Page 117
... SEG2PH<2:0> (CiCFG2<10:8>). The following requirement must be fulfilled while setting the lengths of the phase segments: Prop Seg + Phase1 Seg > = Phase2 Seg © 2011 Microchip Technology Inc. 17.6.5 SAMPLE POINT The sample point is the point of time at which the bus level is read and interpreted as the value of that respec fixed tive bit ...
Page 118
... DS70143E-page 118 © 2011 Microchip Technology Inc. ...
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... Microchip Technology Inc. DS70143E-page 119 ...
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... DS70143E-page 120 © 2011 Microchip Technology Inc. ...
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... DS70143E-page 121 © 2011 Microchip Technology Inc. ...
Page 122
... NOTES: DS70143E-page 122 © 2011 Microchip Technology Inc. ...
Page 123
... CSDOM control bit. This allows other devices to place data on the serial bus during transmission periods not used by the DCI module. © 2011 Microchip Technology Inc. 18.2.3 CSDI PIN The serial data input (CSDI) pin is configured as an input only pin when the module is enabled. ...
Page 124
... DCI Mode Selection bits Receive Buffer Registers w/Shadow Transmit Buffer Registers w/Shadow DS70143E-page 124 BCG Control bits Sample Rate /4 Generator Frame Synchronization Generator DCI Buffer Control Unit 15 DCI Shift Register SCKD CSCK FSD COFS 0 CSDI CSDO © 2011 Microchip Technology Inc. ...
Page 125
... EQUATION 18-1: COFSG PERIOD Frame Length = Word Length • (FSG Value + 1) © 2011 Microchip Technology Inc. Frame lengths data words, may be selected. The frame length in CSCK periods can vary maximum of 256 depending on the word size that is selected ...
Page 126
... LSB S12 S12 S12 Tag Tag Tag bit 2 bit 1 LSb MSb bit 14 bit 13 MSB LSB MSB 2 S protocol does not specify word length – this LSB © 2011 Microchip Technology Inc. ...
Page 127
... When the CSCK signal is applied externally (CSCKD = 1), the BCG<11:0> bits have no effect on the operation of the DCI module. © 2011 Microchip Technology Inc. EQUATION 18-2: The required bit clock frequency will be determined by the system sampling rate and frame size. Typical bit ...
Page 128
... In this case, the buffer control unit counter would be incre- mented twice during a data frame but only one receive register location would be filled with data. © 2011 Microchip Technology Inc. ...
Page 129
... DCI module. © 2011 Microchip Technology Inc. 18.3.16 TRANSMIT STATUS BITS There are two transmit status bits in the DCISTAT SFR. The TMPTY bit is set when the contents of the transmit buffer registers are transferred to the transmit shadow registers ...
Page 130
... The 20-bit AC-Link mode functions similar to the Multi- Channel mode of the DCI module, except for the duty cycle of the frame synchronization signal. The AC-Link frame synchronization signal should remain high for 16 CSCK cycles and should be low for the following 240 cycles. © 2011 Microchip Technology Inc. ...
Page 131
... The user must also select the frame length and data word size using the COFSG and WS control bits in the DCICON2 SFR. © 2011 Microchip Technology Inc. 2 18.7 FRAME AND DATA WORD ...
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... DS70143E-page 132 © 2011 Microchip Technology Inc. ...
Page 133
... AN14 1111 AN15 V AN1 © 2011 Microchip Technology Inc. The ADC module has six 16-bit registers: • ADC Control Register 1 (ADCON1) • ADC Control Register 2 (ADCON2) • ADC Control Register 3 (ADCON3) • ADC Input Select Register (ADCHS) • ADC Port Configuration Register (ADPCFG) • ...
Page 134
... ADCSSL register is ‘1’, the corre- sponding input is selected. The inputs are always scanned from lower to higher numbered inputs, starting after each interrupt. If the number of inputs selected is greater than the number of samples taken per interrupt, the higher numbered inputs are unused. © 2011 Microchip Technology Inc. ...
Page 135
... There are 64 possible options for T EQUATION 19-1: ADC CONVERSION CLOCK (0.5*(ADCS<5:0> © 2011 Microchip Technology Inc. The internal RC oscillator is selected by setting the ADRC bit. For correct ADC conversions, the ADC conversion clock (T ) must be selected to ensure a minimum T AD time of 334 nsec (for V “Electrical Characteristics” ...
Page 136
... Temperature DD s 2.5 kΩ 4.5V -40°C to +85°C to 5.5V ANx 2.5 kΩ 3.0V -40°C to +125°C to 5.5V ANx ANx or V Channels Configuration REF REF CH X S/H ADC REF REF S/H ADC - REF Figure 19-2 for recommended © 2011 Microchip Technology Inc. ...
Page 137
... Set SSRC<2.0> = 111 in the ADCON1 register to enable the auto convert option. • Enable automatic sampling by setting the ASAM control bit in the ADCON1 register. • Write the SMPI<3.0> control bits in the ADCON2 register for the desired number of conversions between interrupts. © 2011 Microchip Technology Inc ...
Page 138
... The internal holding capacitor will discharged state prior to each sample operation ≤ 250Ω IC Sampling Switch leakage V = 0.6V T ± 500 nA PIN AD CONV AD . The combined HOLD , is 2 ≤ 3 kΩ HOLD = DAC capacitance = negligible if Rs ≤ 2.5 kΩ. © 2011 Microchip Technology Inc. ...
Page 139
... Integer 0 © 2011 Microchip Technology Inc. If the ADC interrupt is enabled, the device will wake-up from Sleep. If the ADC interrupt is not enabled, the ADC module will then be turned off, although the ADON bit will remain set ...
Page 140
... Any external components connected (via high-impedance analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. and V as ESD the input voltage exceeds this SS © 2011 Microchip Technology Inc. ...
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... Microchip Technology Inc. DS70143E-page 141 ...
Page 142
... NOTES: DS70143E-page 142 © 2011 Microchip Technology Inc. ...
Page 143
... In the Idle mode, the clock sources are still active, but the CPU is shut-off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2011 Microchip Technology Inc. 20.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 144
... LP oscillator can be conveniently shared as system clock, as well as Real-Time Clock for Timer1. 3: Any higher will violate PLL input range. 4: Any lower will violate PLL input range. 5: Requires external R and C. Frequency operation MHz. DS70143E-page 144 Description (1) (2) (3) (3) (1) (4) (4) (1)(4) (1) (5) /4 output OSC (5) © 2011 Microchip Technology Inc. ...
Page 145
... FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 TUN<3:0> 4 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2011 Microchip Technology Inc. F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Clock Timer ...
Page 146
... OSC2 Function OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 OSC2 0 0 OSC2 1 0 CLKOUT 1 1 CLKOUT OSC2 0 0 (Note (Note (Note © 2011 Microchip Technology Inc. ...
Page 147
... The state of this signal is reflected in the read-only LOCK bit in the OSCCON register. © 2011 Microchip Technology Inc. 20.2.5 FAST RC OSCILLATOR (FRC) The FRC oscillator is a fast (7.37 MHz ±2% nominal) internal RC oscillator ...
Page 148
... Note: The application should not attempt to switch to a clock of frequency lower than 100 kHz when the Fail-Safe Clock Monitor is enabled. If clock switching is performed, the device may generate an oscillator fail trap and switch to the fast RC oscillator. © 2011 Microchip Technology Inc. ...
Page 149
... OSCCON and OSCTUN and one Configuration register, FOSC. Note: The description of the OSCCON and OSCTUN SFRs, as well as the FOSC Configuration register provided in this section are applicable dsPIC30F6011A/6012A/6013A/6014A devices in the dsPIC30F product family. © 2011 Microchip Technology Inc. only to the DS70143E-page 149 ...
Page 150
... Request Oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete DS70143E-page 150 R-y U-0 R/W-y — U-0 R/W-0 U-0 — CF — OSC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. R/W-y R/W-y NOSC<2:0> bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Bit is unknown ...
Page 151
... Center Frequency, Oscillator is running at calibrated frequency 1111 = 1110 = 1101 = 1100 = 1011 = 1010 = 1001 = 1000 = Minimum Frequency © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — TUN<3:0> Unimplemented bit, read as ‘0’ ...
Page 152
... U-0 U-0 R/P — — R/P R/P R/P FPR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Table Table 20-2. © 2011 Microchip Technology Inc. U-0 U-0 — — bit 16 R/P R/P FOS<2:0> bit 8 R/P R/P bit Bit is unknown 20-2. ...
Page 153
... V DD Brown-out Reset BOREN Trap Conflict Illegal Opcode/ Uninitialized W Register © 2011 Microchip Technology Inc. 20.4.1 POR: POWER-ON RESET A power-on event will generate an internal POR pulse when a V rise is detected. The Reset pulse will occur DD at the POR circuit threshold voltage (V nominally 1 ...
Page 154
... Internal POR OST Time-out PWRT Time-out Internal Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR Internal POR OST Time-out PWRT Time-out Internal Reset DS70143E-page 154 T OST T PWRT T OST T PWRT T OST T PWRT ) DD ): CASE CASE 2 DD © 2011 Microchip Technology Inc. ...
Page 155
... The BOR voltage trip points indicated here are nominal values provided for design guidance only. © 2011 Microchip Technology Inc. A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source, based on the device Configuration bit values (FOS<2:0> and FPR< ...
Page 156
... Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. DS70143E-page 156 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( © 2011 Microchip Technology Inc. ...
Page 157
... In some devices, the LVD threshold voltage may be applied externally on the LVDIN pin. The LVD module is enabled by setting the LVDEN bit (RCON<12>). © 2011 Microchip Technology Inc. 20.7 Power-Saving Modes There are two power-saving states that can be entered through the execution of a special instruction, PWRSAV. ...
Page 158
... Specification” (DS70102) and the “dsPIC30F Family Reference Manual” (DS70046). Note: If the code protection Configuration Fuse bits (FBS(BSS<2:0>), FSS(SSS<2:0>), FGS<GSS>, FGS<GWRP>) have been programmed, an erase of the entire code- protected device is only possible at voltages V DD ≥ 4.5V. © 2011 Microchip Technology Inc. ...
Page 159
... Microchip Technology Inc. 20.10 In-Circuit Debugger ® When MPLAB ICD 2 is selected as a debugger, the in-circuit debugging functionality is enabled. This func- tion allows simple debugging functions when used with MPLAB IDE ...
Page 160
... DS70143E-page 160 © 2011 Microchip Technology Inc. ...
Page 161
... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2011 Microchip Technology Inc. Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • The W register (with or without an address modifier) or file register (specified by the value of ‘ ...
Page 162
... Moreover, double word moves require two cycles. The double word instructions execute in two instruction cycles. Note: For more details on the instruction set, refer to the “16-bit MCU and DSC Programmer’s Reference Manual”. Description © 2011 Microchip Technology Inc. ...
Page 163
... Y data space prefetch address register for DSP instructions ∈ {[W10 [W10 [W10 [W10], [W10 [W10 [W10 [W11 [W11 [W11 [W11], [W11 [W11 [W11 [W11 + W12], none} Wyd Y data space prefetch destination register for DSP instructions ∈ {W4..W7} © 2011 Microchip Technology Inc. Description DS70143E-page 163 ...
Page 164
... Branch if Accumulator A overflow Branch if Accumulator B overflow Branch if Overflow Branch if Accumulator A saturated Branch if Accumulator B saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> © 2011 Microchip Technology Inc Status Flags Cycles Affected 1 1 OA,OB,SA, C,DC,N,OV,Z 1 ...
Page 165
... DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 © 2011 Microchip Technology Inc. Description # of Words Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 166
... Move f to WREG Move 16-bit literal to Wn Move 8-bit literal to Wn Move Move Move WREG to f Move Double from W(ns):W( Move Double from Ws to W(nd + 1):W(nd) Prefetch and store accumulator © 2011 Microchip Technology Inc Status Flags Cycles Affected 1 18 N,Z,C,OV 1 ...
Page 167
... RLNC Ws,Wd 65 RRC RRC f RRC f,WREG RRC Ws,Wd © 2011 Microchip Technology Inc. Description # of Words Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) ...
Page 168
... Wn = nibble swap byte swap Wn Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink frame pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-extend Ws © 2011 Microchip Technology Inc Status Flags Cycles Affected N,Z ...
Page 169
... PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits © 2011 Microchip Technology Inc. 22.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...
Page 170
... Support for the entire device instruction set ® standard HEX • Support for fixed-point and floating-point data • Command line interface • Rich directive set • Flexible macro language • MPLAB IDE compatibility © 2011 Microchip Technology Inc. ...
Page 171
... Microchip Technology Inc. 22.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- ...
Page 172
... This usually includes a single application and debug capability, all for DDMAX on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. ® L security ICs, CAN ® © 2011 Microchip Technology Inc. ...
Page 173
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2011 Microchip Technology Inc. (1) (except V and MCLR) ...
Page 174
... Max MIPS dsPIC30F601XA-20E — 20 — 10 — Min Typ Max Unit -40 — +125 °C -40 — +85 °C -40 — +150 °C -40 — +125 ° INT I O θ Typ Max Unit Notes 34 — °C — °C — °C — °C/W 1 © 2011 Microchip Technology Inc. ...
Page 175
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: This is the limit to which V DD © 2011 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min Typ Max 2 ...
Page 176
... OSC1 DD 0.128 MIPS LPRC (512 kHz) (1.8 MIPS) FRC (7.37 MHz) 4 MIPS 10 MIPS 20 MIPS 30 MIPS . DD © 2011 Microchip Technology Inc. ...
Page 177
... Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base I current is measured with Core off, Clock on and all modules turned off. IDLE © 2011 Microchip Technology Inc. ) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° ...
Page 178
... PD (1) Base Power Down Current (2) Watchdog Timer Current: ΔI WDT (2) Timer 1 w/32 kHz Crystal: Δ (2) BOR On: ΔI BOR (2) Low Voltage Detect: ΔI LVD © 2011 Microchip Technology Inc. ...
Page 179
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 5: Negative current is defined as current sourced by the pin. © 2011 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) ...
Page 180
... Industrial A ≤ +125°C for Extended A Units Conditions 8.5 mA 2.0 mA 1.6 mA 2.0 mA -3.0 mA -2.0 mA -1.3 mA -2.0 mA XTL, XT, HS and LP modes when external clock is used to drive OSC1 Osc mode C™ mode © 2011 Microchip Technology Inc. ...
Page 181
... These parameters are characterized but not tested in manufacturing. 2: These values not in usable operating range. FIGURE 23-2: BROWN-OUT RESET CHARACTERISTICS V DD BO10 (Device in Brown-out Reset) Reset (due to BOR) © 2011 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min (2) transition LVDL = 0000 — ...
Page 182
... C ≤ T ≤ +85° Using EECON to read/write V = Minimum operating MIN voltage ms RTSP Provided no other specifications are violated mA Row Erase -40° C ≤ T ≤ +85° Minimum operating MIN voltage RTSP Provided no other specifications are violated mA Row Erase mA Bulk Erase © 2011 Microchip Technology Inc. ...
Page 183
... LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Pin FIGURE 23-4: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT © 2011 Microchip Technology Inc. -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A range as described in DD Load Condition 2 – ...
Page 184
... HS/3 with 4x PLL 25 MHz HS/3 with 8x PLL (3) 22.5 MHz HS/3 with 16x PLL — kHz LP — — See parameter OS10 for F value OSC DC ns See Table 23-16 — — ns See parameter DO31 — ns See parameter DO32 ). CY © 2011 Microchip Technology Inc. ...
Page 185
... AC CHARACTERISTICS Operating temperature Param Characteristic No. OS61 x4 PLL x8 PLL x16 PLL Note 1: These parameters are characterized but not tested in manufacturing. © 2011 Microchip Technology Inc. = 2 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature A -40°C ≤ (1) ...
Page 186
... Industrial ≤ +125°C for Extended Conditions ≤ +85° 3.0-5. ≤ +125° 3.0-5. ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions V = 5.0V, ±10 3.3V, ±10 2.5V DD © 2011 Microchip Technology Inc. ...
Page 187
... Measurements are taken in RC mode and EC mode where CLKOUT output These parameters are characterized but not tested in manufacturing. 4: Data in “Typ” column is at 5V, 25°C unless otherwise stated. © 2011 Microchip Technology Inc. DI35 DI40 New Value DO31 DO32 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 188
... TIMER TIMING CHARACTERISTICS V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal RESET Watchdog Timer RESET I/O Pins SY35 FSCM Delay Note: Refer to Figure 23-3 for load conditions. DS70143E-page 188 SY10 SY20 SY13 SY13 © 2011 Microchip Technology Inc. ...
Page 189
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 3: Characterized by design but not tested 4: Refer to Figure 23-2 and Table 23-11 © 2011 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) Min Typ Max 2 — ...
Page 190
... Band Gap Stable ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions Defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable. RCON<13> Status bit © 2011 Microchip Technology Inc. ...
Page 191
... TCS (T1CON, bit 1)) TA20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note 1: Timer1 is a Type A. © 2011 Microchip Technology Inc. Tx11 Tx10 Tx15 OS60 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 192
... Industrial A -40°C ≤ T ≤ +125°C for Extended A Typ Max Units Conditions — — ns Must also meet parameter TC15 — — ns Must also meet parameter TC15 — — prescale value (1, 8, 64, 256) — 1.5 — © 2011 Microchip Technology Inc. ...
Page 193
... Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2011 Microchip Technology Inc. IC10 IC11 IC15 for load conditions. Standard Operating Conditions: 2.5V to 5.5V ...
Page 194
... OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature Extended (1) (2) Min Typ Max — — — — -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for A Units Conditions ns ns © 2011 Microchip Technology Inc. ...
Page 195
... CSCK (SCKE = 0) CSCK (SCKE = 1) COFS CS55 CS56 CS35 CS51 CS50 HIGH-Z CSDO CSDI Note: Refer to Figure 23-3 for load conditions. © 2011 Microchip Technology Inc MODES) TIMING CHARACTERISTICS CS11 CS10 CS21 CS20 MSb CS30 MSb IN CS40 CS41 CS20 CS21 70 LSb HIGH-Z ...
Page 196
... T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns — ns — ns — — ns — — ns — ns © 2011 Microchip Technology Inc. ...
Page 197
... These parameters are characterized but not tested in manufacturing. 2: These values assume BIT_CLK frequency is 12.288 MHz. 3: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2011 Microchip Technology Inc. CS62 CS21 CS71 CS72 CS76 CS76 Standard Operating Conditions: 2 ...
Page 198
... Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns — ns — ns See parameter DO32 — ns See parameter DO31 — ns See parameter DO32 — ns See parameter DO31 30 ns — ns — ns © 2011 Microchip Technology Inc. ...
Page 199
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2011 Microchip Technology Inc. SP10 SP21 SP35 SP20 LSb BIT14 - - - - - -1 ...
Page 200
... Figure 23-3 for load conditions. -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns — — ns See parameter DO32 — ns See parameter DO31 30 ns — ns — ns — — ns © 2011 Microchip Technology Inc. ...