IC MCU AVR32 128KB FLASH 144LQFP

AT32UC3A0128-ALUT

Manufacturer Part NumberAT32UC3A0128-ALUT
DescriptionIC MCU AVR32 128KB FLASH 144LQFP
ManufacturerAtmel
SeriesAVR®32 UC3
AT32UC3A0128-ALUT datasheets
 


Specifications of AT32UC3A0128-ALUT

Core ProcessorAVRCore Size32-Bit
Speed66MHzConnectivityEBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o109
Program Memory Size128KB (128K x 8)Program Memory TypeFLASH
Ram Size32K x 8Voltage - Supply (vcc/vdd)1.65 V ~ 1.95 V
Data ConvertersA/D 8x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case144-LQFP
Processor SeriesAT32UC3xCoreAVR32
Data Bus Width32 bitData Ram Size32 KB
Interface Type2-Wire, RS-485, SPI, USARTMaximum Clock Frequency66 MHz
Number Of Programmable I/os69Number Of Timers3
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development ToolsEWAVR32, EWAVR32-BL, KSK-EVK1100-PLDevelopment Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature- 40 CController Family/seriesAT32UC3A
No. Of I/o's109Ram Memory Size32KB
Cpu Speed66MHzNo. Of Timers1
Rohs CompliantYesFor Use WithATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
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Features
High Performance, Low Power AVR
– Compact Single-cycle RISC Instruction Set Including DSP Instruction Set
– Read-Modify-Write Instructions and Atomic Bit Manipulation
– Performing 1.49 DMIPS / MHz
Up to 91 DMIPS Running at 66 MHz from Flash (1 Wait-State)
Up to 49 DMIPS Running at 33MHz from Flash (0 Wait-State)
– Memory Protection Unit
Multi-hierarchy Bus System
– High-Performance Data Transfers on Separate Buses for Increased Performance
– 15 Peripheral DMA Channels Improves Speed for Peripheral Communication
Internal High-Speed Flash
– 512K Bytes, 256K Bytes, 128K Bytes Versions
– Single Cycle Access up to 33 MHz
– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
– 4ms Page Programming Time and 8ms Full-Chip Erase Time
– 100,000 Write Cycles, 15-year Data Retention Capability
– Flash Security Locks and User Defined Configuration Area
Internal High-Speed SRAM, Single-Cycle Access at Full Speed
– 64K Bytes (512KB and 256KB Flash), 32K Bytes (128KB Flash)
External Memory Interface on AT32UC3A0 Derivatives
– SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses)
Interrupt Controller
– Autovectored Low Latency Interrupt Service with Programmable Priority
System Functions
– Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator
– Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL) allowing
Independant CPU Frequency from USB Frequency
– Watchdog Timer, Real-Time Clock Timer
Universal Serial Bus (USB)
– Device 2.0 Full Speed and On-The-Go (OTG) Low Speed and Full Speed
– Flexible End-Point Configuration and Management with Dedicated DMA Channels
– On-chip Transceivers Including Pull-Ups
Ethernet MAC 10/100 Mbps interface
– 802.3 Ethernet Media Access Controller
– Supports Media Independent Interface (MII) and Reduced MII (RMII)
One Three-Channel 16-bit Timer/Counter (TC)
– Three External Clock Inputs, PWM, Capture and Various Counting Capabilities
One 7-Channel 16-bit Pulse Width Modulation Controller (PWM)
Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
– Independant Baudrate Generator, Support for SPI, IrDA and ISO7816 interfaces
– Support for Hardware Handshaking, RS485 Interfaces and Modem Line
Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals
One Synchronous Serial Protocol Controller
– Supports I2S and Generic Frame-Based Protocols
One Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible
One 8-channel 10-bit Analog-To-Digital Converter
16-bit Stereo Audio Bitstream
– Sample Rate Up to 50 KHz
®
32 UC 32-Bit Microcontroller
®
AVR
32
32-Bit
Microcontroller
AT32UC3A0512
AT32UC3A0256
AT32UC3A0128
AT32UC3A1512
AT32UC3A1256
AT32UC3A1128
Summary
Preliminary
32058HS–AVR32–03/09

AT32UC3A0128-ALUT Summary of contents

  • Page 1

    ... One Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible • One 8-channel 10-bit Analog-To-Digital Converter • 16-bit Stereo Audio Bitstream – Sample Rate KHz ® 32-Bit Microcontroller ® AVR 32 32-Bit Microcontroller AT32UC3A0512 AT32UC3A0256 AT32UC3A0128 AT32UC3A1512 AT32UC3A1256 AT32UC3A1128 Summary Preliminary 32058HS–AVR32–03/09 ...

  • Page 2

    On-Chip Debug System (JTAG interface) – Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace • 100-pin TQFP (69 GPIO pins), 144-pin LQFP (109 GPIO pins) , 144 BGA (109 GPIO pins) • 5V Input Tolerant I/Os • ...

  • Page 3

    Description The AT32UC3A is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies MHz. AVR32 high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular empha- ...

  • Page 4

    ... Configuration Summary The table below lists all AT32UC3A memory and package configurations: Device AT32UC3A0512 AT32UC3A0256 AT32UC3A0128 AT32UC3A1512 AT32UC3A1256 AT32UC3A1128 3. Abbreviations • GCLK: Power Manager Generic Clock • GPIO: General Purpose Input/Output • HSB: High Speed Bus • MPU: Memory Protection Unit • ...

  • Page 5

    Blockdiagram Figure 4-1. Blockdiagram TC K JTAG TDO INTERFACE O[5..0] M SEO[1..0] EVTI_N EVTO_N VBU S D+ USB D - INTERFACE ID VBO ...

  • Page 6

    Processor and architecture 4.1.1 AVR32 UC CPU • 32-bit load/store AVR32A RISC architecture. – 15 general-purpose 32-bit registers. – 32-bit Stack Pointer, Program Counter and Link Register reside in register file. – Fully orthogonal instruction set. – Privileged and ...

  • Page 7

    Peripheral Bus A able to run on at divided bus speeds compared to the High Speed Bus Figure 4-1 same clock, but the clock to each module can be individually shut off by the Power Manager. The figure identifies ...

  • Page 8

    Signals Description The following table gives details on the signal name classified by peripheral The signals are multiplexed with GPIO pins as described in on page Table 5-1. Signal Description List Signal Name Function VDDPLL Power supply for PLL ...

  • Page 9

    Table 5-1. Signal Description List Signal Name Function MSEO0 - MSEO1 Trace Frame Control EVTI_N Event In EVTO_N Event Out GCLK0 - GCLK3 Generic Clock Pins RESET_N Reset Pin RTC_CLOCK RTC clock WDTEXT External Watchdog Pin EXTINT0 - EXTINT7 External ...

  • Page 10

    Table 5-1. Signal Description List Signal Name Function ADDR0 - ADDR23 Address Bus CAS Column Signal DATA0 - DATA15 Data Bus NCS0 - NCS3 Chip Select NRD Read Signal NWAIT External Wait Signal NWE0 Write Enable 0 NWE1 Write Enable ...

  • Page 11

    Table 5-1. Signal Description List Signal Name Function RX_DATA SSC Receive Data RX_FRAME_SYNC SSC Receive Frame Sync TX_CLOCK SSC Transmit Clock TX_DATA SSC Transmit Data TX_FRAME_SYNC SSC Transmit Frame Sync A0 Channel 0 Line A A1 Channel 1 Line A ...

  • Page 12

    Table 5-1. Signal Description List Signal Name Function AD0 - AD7 Analog input pins ADVREF Analog positive reference voltage input PWM0 - PWM6 PWM Output Pins DDM USB Device Port Data - DDP USB Device Port Data + VBUS USB ...

  • Page 13

    Package and Pinout The device pins are multiplexed with peripheral functions as described in Figure 6-1. TQFP100 Pinout Table 6-1. TQFP100 Package Pinout 1 PB20 2 PB21 3 PB22 4 VDDIO 5 GND 6 PB23 7 PB24 8 PB25 ...

  • Page 14

    Table 6-1. TQFP100 Package Pinout 23 PA02 24 PA03 25 PA04 Figure 6-2. LQFP144 Pinout Table 6-2. VQFP144 Package Pinout 1 PX00 2 PX01 3 PB20 4 PX02 5 PB21 6 PB22 7 VDDIO 8 GND 9 PB23 10 PX03 ...

  • Page 15

    Table 6-2. VQFP144 Package Pinout 22 PB31 23 RESET_N 24 PX05 25 PA00 26 PX06 27 PA01 28 GND 29 VDDCORE 30 PA02 31 PX07 32 PA03 33 PX08 34 PA04 35 PX09 36 VDDIO Figure 6-3. BGA144 Pinout 32058HS–AVR32–03/09 ...

  • Page 16

    Table 6-3. BGA144 Package Pinout A1.. VDDIO PB07 B PB08 GND C PB09 PX33 D PB11 PB13 E PB10 VDDIO F PA30 PB14 G TMS PC03 H TDO VDDCORE J TDI PB17 K PC05 PC04 L PB21 ...

  • Page 17

    Power Considerations 7.1 Power Supplies The AT32UC3A has several types of power supply pins: • VDDIO: Powers I/O lines. Voltage is 3.3V nominal. • VDDANA: Powers the ADC Voltage is 3.3V nominal. • VDDIN: Input voltage for the voltage ...

  • Page 18

    Voltage Regulator 7.2.1 Single Power Supply The AT32UC3A embeds a voltage regulator that converts from 3.3V to 1.8V. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDOUT. VDDOUT should be externally connected to ...

  • Page 19

    Analog-to-Digital Converter (A.D.C) reference. The ADC reference (ADVREF) must be provided from an external source. Two decoupling capacitors must be used to insure proper decoupling. Refer to In case ADC is not used, the ADVREF pin should be connected ...

  • Page 20

    I/O Line Considerations 8.1 JTAG pins TMS, TDI and TCK have pull-up resistors. TDO is an output, driven VDDIO, and has no pull-up resistor. 8.2 RESET_N pin The RESET_N pin is a schmitt input and integrates ...

  • Page 21

    ... Mbyte - 16 Mbyte 16 Mbyte - 16 Mbyte 16 Mbyte - 16 Mbyte 128 Mbyte - 128 Mbyte 64 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte 64 kByte AT32UC3A AT32UC3A1256 AT32UC3A0128 AT32UC3A1128 64 Kbyte 32 Kbyte 32 Kbyte 256 Kbyte 128 Kbyte 128 Kbyte - 16 Mbyte - - 16 Mbyte - - 16 Mbyte - - 128 Mbyte - 64 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte ...

  • Page 22

    ... Kbytes AT32UC3A1256 256 Kbytes AT32UC3A1128 128 Kbytes AT32UC3A0128 128 Kbytes 9.3 Bus Matrix Connections Accesses to unused areas returns an error result to the master requesting such an access. The bus matrix has the several masters and slaves. Each master has its own bus and its own decoder, thus allowing a different memory mapping per master ...

  • Page 23

    Figure 9-1. 32058HS–AVR32–03/09 HMatrix Master / Slave Connections 0 1 CPU Data 0 CPU 1 Instruction CPU SAB 2 PDCA 3 MACB 4 USBB DMA 5 AT32UC3A HMATRIX SLAVES ...

  • Page 24

    Peripherals 10.1 Peripheral address map Table 10-1. Peripheral Address Mapping Address 0xE0000000 0xFFFE0000 0xFFFE1000 0xFFFE1400 0xFFFE1800 0xFFFE1C00 0xFFFE2000 0xFFFF0000 0xFFFF0800 0xFFFF0C00 0xFFFF0D00 0xFFFF0D30 0xFFFF0D80 0xFFFF1000 0xFFFF1400 0xFFFF1800 32058HS–AVR32–03/09 Peripheral Name USBB USBB Slave Interface - USBB USBB USBB Configuration ...

  • Page 25

    Table 10-1. Peripheral Address Mapping (Continued) Address 0xFFFF1C00 0xFFFF2000 0xFFFF2400 0xFFFF2800 0xFFFF2C00 0xFFFF3000 0xFFFF3400 0xFFFF3800 0xFFFF3C00 10.2 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being ...

  • Page 26

    The following GPIO registers are mapped on the local bus: Table 10-2. Port 32058HS–AVR32–03/09 Local bus mapped GPIO registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Output Driver Enable Register ...

  • Page 27

    Table 10-2. Port 3 10.3 Interrupt Request Signal Map The various modules may output Interrupt request signals. These signals are routed to the Inter- rupt Controller (INTC), described in a later chapter. The Interrupt Controller supports groups ...

  • Page 28

    Table 10-3. 32058HS–AVR32–03/09 Interrupt Request Signal Map 0 General Purpose Input/Output 1 General Purpose Input/Output 2 General Purpose Input/Output 3 General Purpose Input/Output 4 General Purpose Input/Output 5 General Purpose Input/Output 6 General Purpose Input/Output 2 7 General Purpose Input/Output ...

  • Page 29

    Table 10-3. 10.4 Clock Connections 10.4.1 Timer/Counters Each Timer/Counter channel can independently select an internal or external clock source for its counter: Table 10-4. Source Internal External 10.4.2 USARTs Each USART can be connected to an internally divided clock: Table ...

  • Page 30

    SPIs Each SPI can be connected to an internally divided clock: Table 10-6. SPI 0 1 10.5 Nexus OCD AUX port connections If the OCD trace system is enabled, the trace system will take control over a number of ...

  • Page 31

    Table 10-8. PID Value 10.7 Peripheral Multiplexing on I/O lines Each GPIO line can be assigned to one of 3 peripheral functions ...

  • Page 32

    Table 10-9. GPIO Controller Function Multiplexing 41 58 PA16 42 60 PA17 43 62 PA18 44 64 PA19 45 66 PA20 51 73 PA21 52 74 PA22 53 75 PA23 54 76 PA24 55 77 PA25 56 78 PA26 57 ...

  • Page 33

    Table 10-9. GPIO Controller Function Multiplexing 7 11 PB24 8 13 PB25 9 14 PB26 10 15 PB27 14 19 PB28 15 20 PB29 16 21 PB30 17 22 PB31 63 85 PC00 64 86 PC01 85 124 PC02 86 ...

  • Page 34

    Table 10-9. GPIO Controller Function Multiplexing 99 PX25 101 PX26 103 PX27 105 PX28 107 PX29 110 PX30 112 PX31 114 PX32 118 PX33 120 PX34 135 PX35 137 PX36 140 PX37 142 PX38 144 PX39 10.8 Oscillator Pinout The ...

  • Page 35

    GPIO The GPIO open drain feature (GPIO ODMER register (Open Drain Mode Enable Register)) is not available for this device. 10.11 Peripheral overview 10.11.1 External Bus Interface • Optimized for Application Memory Space support • Integrates Two External Memory ...

  • Page 36

    Supports Mobile SDRAM Devices • Error Detection – Refresh Error Interrupt • SDRAM Power-up Initialization by Software • CAS Latency Supported • Auto Precharge Command Not Used 10.11.4 USB Controller • USB 2.0 Compliant, Full-/Low-Speed ...

  • Page 37

    Optional Manchester Encoding • RS485 with driver control signal • ISO7816 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation ...

  • Page 38

    Ethernet 10/100 MAC • Compatibility with IEEE Standard 802.3 • 10 and 100 Mbits per second data throughput capability • Full- and half-duplex operations • MII or RMII interface to the physical layer • Register Interface to address, data, ...

  • Page 39

    Boot Sequence This chapter summarizes the boot sequence of the AT32UC3A. The behaviour after power-up is controlled by the Power Manager. For specific details, refer to (PM)” on page 11.1 Starting of clocks After power-up, the device will be ...

  • Page 40

    Electrical Characteristics 12.1 Absolute Maximum Ratings* Operating Temperature......................................-40⋅C to +85⋅C Storage Temperature ..................................... -60°C to +150°C Voltage on Input Pin with respect to Ground except for PC00, PC01, PC02, PC03, PC04, PC05..........................................................-0.3V to 5.5V Voltage on Input Pin with ...

  • Page 41

    DC Characteristics The following characteristics are applicable to the operating temperature range: T ified and are certified for a junction temperature Table 12-1. DC Characteristics Symbol Parameter V VDDCOR DC Supply Core Supply ...

  • Page 42

    Regulator characteristics Table 12-2. Symbol Parameter V Supply voltage (input) VDDIN V Supply voltage (output) VDDOUT Maximum DC output current with V I OUT Maximum DC output current with V I Static Current of internal regulator SCR Table 12-3. ...

  • Page 43

    Table 12-7. Symbol T BOD 12.4.2 POR Table 12-8. Symbol Parameter VDDCORE rise rate to ensure power-on-reset V DDRR V VDDCORE fall rate to ensure power-on-reset SSFR Rising threshold voltage: voltage up to which device is kept under reset by ...

  • Page 44

    Power Consumption The values in tion with operating conditions as follows: •V DDIO •V DDCORE •T = 25° •I/Os are configured in input, pull-up enabled. Figure 12-1. Measurement setup 32058HS–AVR32–03/09 Table 12-9 and Table 12-10 on page ...

  • Page 45

    These figures represent the power consumption measured on the power supplies. Table 12-9. Power Consumption for Different Modes Mode Conditions Typ : Ta =25 °C CPU running from flash VDDIN=3.3 V. VDDCORE =1.8V. CPU clocked from PLL0 at f MHz ...

  • Page 46

    Table 12-9. Power Consumption for Different Modes Mode Conditions Typ : °C. CPU is in stop mode GPIOs on internal pull-up. Stop All peripheral clocks de-activated. DM and DP pins connected to ground. XIN0,Xin1 and XIN2 are ...

  • Page 47

    V DDCORE • Ambient Temperature = 25°C 12.6.1 CPU/HSB Clock Characteristics Table 12-11. Core Clock Waveform Parameters Symbol Parameter 1/(t ) CPU Clock Frequency CPCPU t CPU Clock Period CPCPU 12.6.2 PBA Clock Characteristics Table 12-12. PBA Clock Waveform ...

  • Page 48

    Main Oscillators Characteristics Table 12-15. Main Oscillator Characteristics Symbol Parameter 1/(t ) Crystal Oscillator Frequency CPMAIN Internal Load Capacitance Duty Cycle t Startup Time ST 1/(t ) XIN ...

  • Page 49

    ADC Characteristics Table 12-17. Channel Conversion Time and ADC Clock Parameter ADC Clock Frequency ADC Clock Frequency Startup Time Track and Hold Acquisition Time Conversion Time Conversion Time Throughput Rate Throughput Rate Notes: 1. Corresponds to 13 clock cycles ...

  • Page 50

    Table 12-21. Transfer Characteristics in 10-bit mode Parameter Resolution Absolute Accuracy Integral Non-linearity Differential Non-linearity Offset Error Gain Error 32058HS–AVR32–03/09 Conditions Min f=5MHz f=5MHz f=5MHz f=2.5MHz f=5MHz -2 f=5MHz -2 AT32UC3A Typ Max Units 10 Bit 3 LSB 1.5 2 ...

  • Page 51

    EBI Timings These timings are given for worst case process 85⋅C, VDDCORE = 1.65V, VDDIO = 3V and 40 pF load capacitance. Table 12-22. SMC Clock Signal. Symbol Parameter 1/(t ) SMC Controller Clock Frequency CPSMC Note: ...

  • Page 52

    Table 12-24. SMC Read Signals with no Hold Settings Symbol Parameter SMC Data Setup before NRD High 19 Data Hold after NRD High SMC 20 SMC Data Setup before NCS High 21 SMC Data Hold after NCS High 22 Table ...

  • Page 53

    Table 12-26. SMC Write Signals with No Hold Settings (NWE Controlled only). Symbol Parameter NWE Rising to A2-A25 Valid SMC 37 NWE Rising to NBS0/A0 Valid SMC 38 NWE Rising to NBS1 Change SMC 39 NWE Rising to A1/NBS2 Change ...

  • Page 54

    Figure 12-3. SMC Signals for NRD and NRW Controlled Accesses. A2-A25 A0/A1/NBS[3:0] NCS SMC9 NRD SMC19 D0 - D15 NWE 12.9.1 SDRAM Signals These timings are given for 10 pF load on SDCK and other signals. Table ...

  • Page 55

    Table 12-28. SDRAM Clock Signal. Symbol SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC 32058HS–AVR32–03/09 Parameter Address Change before SDCK Rising Edge 11 Address Change after SDCK Rising Edge 12 Bank Change before SDCK ...

  • Page 56

    Figure 12-4. SDRAMC Signals relative to SDCK. SDCK SDRAMC SDRAMC SDRAMC 1 2 SDCKE SDCS RAS CAS SDWE SDA10 A0 - A9, A11 - A13 BA0/BA1 DQM0 - DQM3 D0 - D15 Read D0 - D15 to Write 32058HS–AVR32–03/09 SDRAMC ...

  • Page 57

    JTAG Timings 12.10.1 JTAG Interface Signals Table 12-29. JTAG Interface Timing specification Symbol Parameter JTAG TCK Low Half-period 0 JTAG TCK High Half-period 1 JTAG TCK Period 2 JTAG TDI, TMS Setup before TCK High 3 JTAG TDI, TMS ...

  • Page 58

    Figure 12-5. JTAG Interface Signals TCK TMS/TDI TDO Device Inputs Device Outputs 12.11 SPI Characteristics Figure 12-6. SPI Master mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) SPCK MISO MOSI 32058HS–AVR32–03/09 JTAG 2 JTAG 0 JTAG JTAG ...

  • Page 59

    Figure 12-7. SPI Master mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) SPCK MISO MOSI Figure 12-8. SPI Slave mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) SPCK MISO MOSI Figure 12-9. SPI Slave mode with (CPOL = ...

  • Page 60

    Table 12-30. SPI Timings Symbol Parameter SPI MISO Setup time before SPCK rises (master) 0 SPI MISO Hold time after SPCK rises (master) 1 SPI SPCK rising to MOSI Delay (master) 2 SPI MISO Setup time before SPCK falls (master) ...

  • Page 61

    Table 12-32. Ethernet MAC MII Specific Signals Symbol Parameter EMAC Hold for ERX from ERXCK 12 EMAC Setup for ERXER from ERXCK 13 EMAC Hold for ERXER from ERXCK 14 EMAC Setup for ERXDV from ERXCK 15 EMAC Hold for ...

  • Page 62

    Table 12-33. Ethernet MAC RMII Specific Signals Symbol EMAC EMAC EMAC EMAC EMAC EMAC EMAC EMAC Figure 12-11. Ethernet MAC RMII Mode EREFCK ETXEN ETX[1:0] ERX[1:0] ERXER ECRSDV 12.13 Flash Characteristics The following table gives the device maximum operating frequency ...

  • Page 63

    Table 12-35. Programming Time Temperature Operating Range Part Industrial Automotive 32058HS–AVR32–03/09 Page Programming Time (ms AT32UC3A Chip Erase Time (ms ...

  • Page 64

    Mechanical Characteristics 13.1 Thermal Considerations 13.1.1 Thermal Data Table 13-1 Table 13-1. Symbol θ JA θ JC θ JA θ JC 13.1.2 Junction Temperature The average chip-junction temperature where: • θ = package thermal ...

  • Page 65

    Package Drawings Figure 13-1. TQFP-100 package drawing Table 13-2. Device and Package Maximum Weight 500 Table 13-3. Package Characteristics Moisture Sensitivity Level Table 13-4. Package Reference JEDEC Drawing Reference JESD97 Classification 32058HS–AVR32–03/09 mg Jdec J-STD0-20D - MSL 3 MS-026 ...

  • Page 66

    Figure 13-2. LQFP-144 package drawing Table 13-5. Device and Package Maximum Weight 1300 Table 13-6. Package Characteristics Moisture Sensitivity Level Table 13-7. Package Reference JEDEC Drawing Reference JESD97 Classification 32058HS–AVR32–03/09 mg Jdec J-STD0-20D - MSL 3 MS-026 E3 AT32UC3A 66 ...

  • Page 67

    Figure 13-3. FFBGA-144 package drawing Table 13-8. Device and Package Maximum Weight TBD Table 13-9. Package Characteristics Moisture Sensitivity Level Table 13-10. Package Reference JEDEC Drawing Reference JESD97 Classification 32058HS–AVR32–03/09 mg TBD MS-026 E3 AT32UC3A 67 ...

  • Page 68

    Soldering Profile Table 13-11 Table 13-11. Soldering Profile Profile Feature Average Ramp-up Rate (217°C to Peak) Preheat Temperature 175°C ±25°C Time Maintained Above 217°C Time within 5⋅C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25⋅C to ...

  • Page 69

    ... Ordering Code AT32UC3A0512 AT32UC3A0512-ALUT AT32UC3A0512-ALUR AT32UC3A0512-ALTR AT32UC3A0512-ALTT AT32UC3A0512-ALTES AT32UC3A0512-CTUT AT32UC3A0512-CTUR AT32UC3A0256 AT32UC3A0256-ALUT AT32UC3A0256-ALUR AT32UC3A0256-CTUT AT32UC3A0256-CTUR AT32UC3A0128 AT32UC3A0128-ALUT AT32UC3A0128-ALUR AT32UC3A0128-CTUT AT32UC3A0128-CTUR AT32UC3A1512 AT32UC3A1512-AUT AT32UC3A1512-AUR AT32UC3A1256 AT32UC3A1256-AUT AT32UC3A1256-AUR AT32UC3A1128 AT32UC3A1128-AUT AT32UC3A1128-AUR 14.1 Automotive Quality Grade The AT32UC3A have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949 ...

  • Page 70

    Errata All industrial parts labelled with -UES (engineering samples) are revision E parts. 15.1 Rev. K 15.1.1 PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), ...

  • Page 71

    SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and NCPHA=0 When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and ...

  • Page 72

    For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer ...

  • Page 73

    Rev. J 15.2.1 PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and ...

  • Page 74

    When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 4. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first ...

  • Page 75

    None. 15.2.9 USART 1. ISO7816 info register US_NER cannot be read The NER register always returns zero. Fix/Workaround None 15.2.10 Processor and Architecture 1. LDM instruction with PC in the register list and without ++ increments Rp For LDM with ...

  • Page 76

    Rev. I 15.3.1 PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and ...

  • Page 77

    When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 4. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first ...

  • Page 78

    Workaround/fix The same PID should not be assigned to more than one channel. 15.3.7 GPIO 1. Some GPIO VIH (input high voltage) are 3.6V max instead of 5V tolerant Only 11 GPIOs remain 5V tolerant (VIHmax=5V):PB01, PB02, PB03, PB10, PB19, ...

  • Page 79

    Execute the RETE instruction. 32058HS–AVR32–03/09 AT32UC3A 79 ...

  • Page 80

    Rev. H 15.4.1 PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and ...

  • Page 81

    SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and NCPHA=0 When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and ...

  • Page 82

    This may lead to an exception or to other errors derived from this corrupted read access. Fix/Workaround Flashc WP, EP, EA, WUP, EUP commands: ...

  • Page 83

    RETS behaves incorrectly when MPU is enabled and MPU is configured so that system stack is not readable in unprivileged mode. Fix/Woraround Workaround 1: Make system stack readable in unprivileged mode, or Workaround 2: Return from supervisor mode using rete ...

  • Page 84

    Rev. E 15.5.1 SPI 1. SPI FDIV option does not work Selecting clock signal using FDIV = 1 does not work as specified. Fix/Workaround Do not set FDIV = 1. 2. SPI Slave / PDCA transfer UNDERRUN ...

  • Page 85

    Fix/workaround When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 15.5.2 PWM 1. PWM counter restarts at 0x0001 The PWM counter restarts at 0x0001 and not ...

  • Page 86

    USB 1. USB No end of host reset signaled upon disconnection In host mode, in case of an unexpected device disconnection whereas a usb reset is being sent by the usb controller, the UHCON.RESET bit may not been cleared ...

  • Page 87

    CPU Cycle Counter does not reset the COUNT system register on COMPARE match. The device revision E does not reset the COUNT system register on COMPARE match. In this revision, the COUNT register is clocked by the CPU clock, ...

  • Page 88

    CPU cannot operate on a divided slow clock (internal RC oscillator) Fix/Workaround Do not run the CPU on a divided slow clock. 13. LDM instruction with PC in the register list and without ++ increments Rp For LDM with ...

  • Page 89

    USART RXBREAK problem when no timeguard In asynchronous mode the RXBREAK flag is not correctly handled when the timeguard is 0 and the break character is located just after the stop bit. Fix/Workaround If the NBSTOP is 1, timeguard ...

  • Page 90

    Fix/Workaround In PLL0/1 Control register, the bit 7 should be set in order to prevent unexpected behaviour. 4. Peripheral Bus A maximum frequency is 33MHz instead of 66MHz. Fix/Workaround Do not set PBA frequency higher than 33 MHz. 5. PCx ...

  • Page 91

    If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode before after the next AD conversion. Fix/Workaround Activate the sleep mode in the mode register and then perform an AD conversion. ...

  • Page 92

    The RTC CLKEN bit (bit number 16) of CTRL register is not available. Fix/Workaround Do not use the CLKEN bit of the RTC on Rev E. 15.5.14 OCD 1. Stalled memory access instruction writeback fails if followed by a ...

  • Page 93

    Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 16.1 Rev. H – 03/ 16.2 ...

  • Page 94

    Rev. C – 10/ 16.7 Rev. B – 10/ 16.8 Rev. A – 03/07 1. 32058HS–AVR32–03/09 Updated ”Signal Description List” on page USART section. Updated ”Errata” on page 70. Rev ...

  • Page 95

    Table of Contents 1 Description ............................................................................................... 3 2 Configuration Summary .......................................................................... 4 3 Abbreviations ........................................................................................... 4 4 Blockdiagram ........................................................................................... 5 5 Signals Description ................................................................................. 8 6 Package and Pinout ............................................................................... 13 7 Power Considerations ........................................................................... 17 8 I/O Line Considerations ...

  • Page 96

    Boot Sequence ....................................................................................... 39 11.1Starting of clocks ...................................................................................................39 11.2Fetching of initial instructions ................................................................................39 12 Electrical Characteristics ...................................................................... 40 12.1Absolute Maximum Ratings* .................................................................................40 12.2DC Characteristics ................................................................................................41 12.3Regulator characteristics .......................................................................................42 12.4Analog characteristics ...........................................................................................42 12.5Power Consumption ..............................................................................................44 12.6Clock Characteristics ...

  • Page 97

    E – 04/08 .......................................................................................................93 16.5Rev. D – 04/08 ......................................................................................................93 16.6Rev. C – 10/07 ......................................................................................................94 16.7Rev. B – 10/07 .......................................................................................................94 16.8Rev. A – 03/07 .......................................................................................................94 AT32UC3A III ...

  • Page 98

    ... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...