C8051F305-GS Silicon Laboratories Inc, C8051F305-GS Datasheet - Page 27

• Manufacturer Part Number: C8051F305-GS
• Description: IC 8051 MCU 2K FLASH 14-SOIC
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F305-GS

• Program Memory Type: FLASH
• Program Memory Size: 2KB (2K x 8)
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SMBus/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F300DK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1444 - ADAPTER PROGRAM TOOLSTICK F300
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1540-5

4.
N.C. pins for F30x GP packages: 4, 9, 11
CNVSTR
XTAL1 /
XTAL2 /
VREF /
C2CK /
Name
P0.6 /
C2D /
GND
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.7
RST
V
DD
Pinout and Package Definitions
F300/1/2/3/4/5
GM
Pin
10
11
1
2
3
4
5
6
7
8
9
Table 4.1. Pin Definitions for the C8051F300/1/2/3/4/5
F300/1/2/3/4/5
Pin
GP
10
12
13
14
5
6
7
8
1
2
3
D I/O or
D I/O or
D I/O or
D I/O or
D I/O or
D I/O or
D I/O or
A Out
D I/O
D I/O
D I/O
D I/O
Type
D I/O
A In
A In
A In
A In
A In
A In
A In
A In
A In
Rev. 2.9
External Voltage Reference Input.
Port 0.0. See
Port 0.1. See
Power Supply Voltage.
Crystal Input. This pin is the external oscillator cir-
cuit return for a crystal or ceramic resonator. See
Section
Port 0.2. See
Crystal Input/Output. For an external crystal or res-
onator, this pin is the excitation driver. This pin is
the external clock input for CMOS, capacitor, or RC
network configurations. See
Port 0.3. See
Port 0.4. See
Port 0.5. See
Clock signal for the C2 Development Interface.
Device Reset. Open-drain output of internal POR or
V
tem reset by driving this pin low for at least 10 µs.
Port 0.6. See
ADC External Convert Start Input Strobe.
Data signal for the C2 Development Interface.
Port 0.7. See
Ground.
DD
monitor. An external source can initiate a sys-
11.2.
C8051F300/1/2/3/4/5
Section 12
Section 12
Section 12
Section 12
Section 12
Section 12
Section 12
Section 12
Description
for complete description.
for complete description.
for complete description.
for complete description.
for complete description.
for complete description.
for complete description.
for complete description.
Section
11.2.
27