C8051F337-GM Silicon Laboratories Inc, C8051F337-GM Datasheet - Page 100

• Manufacturer Part Number: C8051F337-GM
• Description: IC MCU 16K FLASH 20QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F33xr

Specifications of C8051F337-GM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QFN
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F336DK
• Minimum Operating Temperature: - 40 C
• For Use With: 336-1451 - ADAPTER PROGRAM TOOLSTICK F330
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1428-5

C8051F336/7/8/9
17. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. Upon entering this
reset state, the following events occur:
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled dur-
ing and after the reset. For V
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source. Pro-
gram execution begins at location 0x0000.
100
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
Px.x
Px.x
System
Clock
Comparator 0
+
-
Detector
Missing
C0RSEF
Clock
(one-
shot)
Microcontroller
EN
DD
Extended Interrupt
CIP-51
Monitor and power-on resets, the RST pin is driven low until the device
Core
Handler
Figure 17.1. Reset Sources
WDT
PCA
EN
VDD
System Reset
Supply
Monitor
+
-
Rev.1.0
Enable
(Software Reset)
SWRSF
'0'
Power On
Reset
Operation
FLASH
Errant
(wired-OR)
Reset
Funnel
/RST