C8051F360-GQ Silicon Laboratories Inc, C8051F360-GQ Datasheet
C8051F360-GQ
Specifications of C8051F360-GQ
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C8051F360-GQ Summary of contents
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... Flexible PLL technology - External oscillator: Crystal, RC clock ( pin modes) - Can switch between clock sources on-the-fly; useful in power saving modes Packages - 48-pin TQFP (C8051F360/3) - 32-pin LQFP (C8051F361/4/6/8) - 28-pin QFN (C8051F362/5/7/9) Temperature Range: –40 to +85 °C ANALOG DIGITAL I/O PERIPHERALS UART + SMBus ...
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... C8051F360/1/2/3/4/5/6/7/8/9 2 Rev. 1.0 ...
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... Settling Time Requirements ..................................................................... 53 5.4. Programmable Window Detector ...................................................................... 58 5.4.1. Window Detector In Single-Ended Mode ................................................. 60 5.4.2. Window Detector In Differential Mode...................................................... 61 6. 10-Bit Current Mode DAC (IDA0, C8051F360/1/2/6/7/8/9) .................................... 63 6.1. IDA0 Output Scheduling ................................................................................... 63 6.1.1. Update Output On-Demand ..................................................................... 63 6.1.2. Update Output Based on Timer Overflow ................................................ 64 6.1.3. Update Output Based on CNVSTR Edge................................................. 64 6 ...
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... C8051F360/1/2/3/4/5/6/7/8/9 9.4.3. General Purpose Registers ...................................................................... 87 9.4.4. Bit Addressable Locations........................................................................ 87 9.4.5. Stack ....................................................................................................... 87 9.4.6. Special Function Registers....................................................................... 88 9.4.7. Register Descriptions ............................................................................. 102 9.5. Power Management Modes ............................................................................ 104 9.5.1. Idle Mode................................................................................................ 105 9.5.2. Stop Mode .............................................................................................. 105 9.5.3. Suspend Mode ....................................................................................... 105 10. Interrupt Handler .................................................................................................. 107 10.1.MCU Interrupt Sources and Vectors............................................................... 107 10 ...
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... Input Clock and Pre-divider ............................................................ 178 16.8.2.PLL Multiplication and Output Clock ...................................................... 178 16.8.3.Powering on and Initializing the PLL ...................................................... 179 17. Port Input/Output.................................................................................................. 183 17.1.Priority Crossbar Decoder .............................................................................. 185 17.2.Port I/O Initialization ....................................................................................... 187 17.3.General Purpose Port I/O ............................................................................... 190 18. SMBus ................................................................................................................... 202 18.1.Supporting Documents ................................................................................... 203 18.2.SMBus Configuration...................................................................................... 203 C8051F360/1/2/3/4/5/6/7/8/9 Rev. 1.0 5 ...
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... C8051F360/1/2/3/4/5/6/7/8/9 18.3.SMBus Operation ........................................................................................... 203 18.3.1.Arbitration............................................................................................... 204 18.3.2.Clock Low Extension.............................................................................. 204 18.3.3.SCL Low Timeout................................................................................... 204 18.3.4.SCL High (SMBus Free) Timeout .......................................................... 205 18.4.Using the SMBus............................................................................................ 205 18.4.1.SMBus Configuration Register............................................................... 206 18.4.2.SMB0CN Control Register ..................................................................... 209 18.4.3.Data Register ......................................................................................... 212 18.5.SMBus Transfer Modes.................................................................................. 213 18.5.1.Master Transmitter Mode ....................................................................... 213 18 ...
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... Timer Usage ......................................................................... 274 22.4.Register Descriptions for PCA0...................................................................... 276 23. Revision Specific Behavior ................................................................................. 281 23.1.Revision Identification..................................................................................... 281 23.2.C2D Port Pin Requirements ........................................................................... 283 24. C2 Interface ........................................................................................................... 284 24.1.C2 Interface Registers.................................................................................... 284 24.2.C2 Pin Sharing ............................................................................................... 286 Document Change List ............................................................................................. 287 Contact Information .................................................................................................. 288 C8051F360/1/2/3/4/5/6/7/8/9 Rev. 1.0 7 ...
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... C8051F360/1/2/3/4/5/6/7/8/9 List of Figures 1. System Overview Figure 1.1. C8051F360/3 Block Diagram ................................................................. 20 Figure 1.2. C8051F361/4/6/8 Block Diagram ........................................................... 21 Figure 1.3. C8051F362/5/7/9 Block Diagram ........................................................... 21 Figure 1.4. Comparison of Peak MCU Execution Speeds ....................................... 22 Figure 1.5. On-Chip Clock and Reset ......................................................................23 Figure 1.6. On-Board Memory Map ......................................................................... 24 Figure 1.7. Development/In-System Debug Diagram .............................................. 25 Figure 1 ...
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... Figure 17.1. Port I/O Functional Block Diagram (Port 0 through Port 3) ............... 183 Figure 17.2. Port I/O Cell Block Diagram .............................................................. 184 Figure 17.3. Crossbar Priority Decoder with No Pins Skipped .............................. 185 Figure 17.4. Crossbar Priority Decoder with Port Pins Skipped ............................ 186 C8051F360/1/2/3/4/5/6/7/8/9 Rev. 1.0 9 ...
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... C8051F360/1/2/3/4/5/6/7/8/9 18. SMBus Figure 18.1. SMBus Block Diagram ...................................................................... 202 Figure 18.2. Typical SMBus Configuration ............................................................ 203 Figure 18.3. SMBus Transaction ........................................................................... 204 Figure 18.4. Typical SMBus SCL Generation ........................................................ 207 Figure 18.5. Typical Master Transmitter Sequence ............................................... 213 Figure 18.6. Typical Master Receiver Sequence ................................................... 214 Figure 18.7. Typical Slave Receiver Sequence ..................................................... 215 Figure 18 ...
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... Figure 22.10. PCA Module 5 with Watchdog Timer Enabled ................................ 273 23. Revision Specific Behavior Figure 23.1. Device Package - TQFP 48 ............................................................... 281 Figure 23.2. Device Package - LQFP 32 ............................................................... 282 Figure 23.3. Device Package - QFN 28 ................................................................. 282 24. C2 Interface Figure 24.1. Typical C2 Pin Sharing ...................................................................... 286 C8051F360/1/2/3/4/5/6/7/8/9 Rev. 1.0 11 ...
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... Table 13.1. Flash Security Summary .................................................................... 139 Table 13.2. Flash Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 14. Branch Target Cache 15. External Data Memory Interface and On-Chip XRAM Table 15.1. EMIF Pinout (C8051F360/3) ............................................................... 155 Table 15.2. AC Parameters for External Memory Interface ................................... 168 16. Oscillators Table 16.1. Internal High Frequency Oscillator Electrical Characteristics . . . . . . . 171 Table 16 ...
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... Table 20.1. SPI Slave Timing Parameters ............................................................ 246 21. Timers 22. Programmable Counter Array Table 22.1. PCA Timebase Input Options ............................................................. 265 Table 22.2. PCA0CPM Register Settings for PCA Capture/Compare Modules .... 267 Table 22.3. Watchdog Timer Timeout Intervals ..................................................... 275 23. Revision Specific Behavior 24. C2 Interface C8051F360/1/2/3/4/5/6/7/8/9 Rev. 1.0 13 ...
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... C8051F360/1/2/3/4/5/6/7/8/9 List of Registers SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . . 54 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select . . . . . . . . . . . . . . . . . . 55 SFR Definition 5.3. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 SFR Definition 5.4. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 56 SFR Definition 5.5. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 SFR Definition 5 ...
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... SFR Definition 17.10. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 SFR Definition 17.11. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 194 SFR Definition 17.12. P1SKIP: Port1 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 SFR Definition 17.13. P1MAT: Port1 Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 SFR Definition 17.14. P1MASK: Port1 Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 SFR Definition 17.15. P2: Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 C8051F360/1/2/3/4/5/6/7/8 152 Rev. 1.0 15 ...
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... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.16. P2MDIN: Port2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 SFR Definition 17.17. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 196 SFR Definition 17.18. P2SKIP: Port2 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 SFR Definition 17.19. P2MAT: Port2 Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 SFR Definition 17.20. P2MASK: Port2 Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 SFR Definition 17.21. P3: Port3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 SFR Definition 17 ...
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... C2 Register Definition 24.2. DEVICEID: C2 Device 284 C2 Register Definition 24.3. REVID: C2 Revision 285 C2 Register Definition 24.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 285 C2 Register Definition 24.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 285 C8051F360/1/2/3/4/5/6/7/8/9 Rev. 1.0 17 ...
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... C8051F360/1/2/3/4/5/6/7/8/9 1. System Overview C8051F36x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection. • High-speed pipelined 8051-compatible microcontroller core (up to 100 MIPS) • In-system, full-speed, non-intrusive debug interface (on-chip) • ...
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... Table 1.1. Product Selection Guide C8051F360-GQ 100 32 1024 100 32 1024 1 C8051F361-GQ 100 32 1024 2 C8051F362-GM C8051F363-GQ 100 32 1024 100 32 1024 1 C8051F364-GQ 2 100 32 1024 C8051F365- 1024 C8051F366- 1024 C8051F367- 1024 C8051F368- 1024 C8051F369-GM Notes: 1. Pin compatible with the C8051F310-GQ. 2. Pin compatible with the C8051F311-GM. ...
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... Net 1 kB XRAM GND 2-cycle Multiply and Accumulate System Clock Setup XTAL1 External XTAL2 Oscillator Multiplier Internal Oscillator Low Frequency Oscillator Figure 1.1. C8051F360/3 Block Diagram 20 Port I/O Configuration Digital Peripherals UART0 Timers Priority Crossbar PCA/WDT Decoder SMBus SPI Crossbar Control ...
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... GND 2-cycle Multiply and Accumulate System Clock Setup XTAL1 External Oscillator XTAL2 Clock Multiplier Internal Oscillator Low Frequency Oscillator Figure 1.3. C8051F362/5/7/9 Block Diagram C8051F360/1/2/3/4/5/6/7/8/9 Port I/O Configuration Digital Peripherals Port 0 Drivers UART0 Timers Priority Port 1 Crossbar Drivers PCA/WDT Decoder SMBus ...
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... C8051F360/1/2/3/4/5/6/7/8/9 1.1. CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F36x family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052, including ...
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... Frequency Oscillator Internal Oscillator System Clock PLL Circuitry External XTAL1 Oscillator Clock Select XTAL2 Drive Figure 1.5. On-Chip Clock and Reset C8051F360/1/2/3/4/5/6/7/8/9 as given in Table 12.1 on page 134), a Watchdog Timer, a RST VDD Supply Monitor + - Enable C0RSEF Missing Clock Detector (one- PCA shot) ...
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... Program memory consists of 32/ Flash. This memory may be reprogrammed in-system in 1024 byte sectors, and requires no special off-chip programming voltage. See Figure 1.6 for the MCU system memory map. PROGRAM MEMORY C8051F360/1/2/3/4/5/6/7 RESERVED 0x7C00 0x7BFF FLASH ...
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... All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single stepping breakpoint in order to keep them synchronized. The C8051F360DK development kit provides all the hardware and software necessary to develop applica- tion code and perform in-circuit debugging with the C8051F36x MCUs. The kit includes software with a developer's studio and debugger, an integrated 8051 assembler, and a debug adapter ...
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... PnMDIN Registers Decoder P0 8 I/O Cells P1 8 Digital I/O Crossbar Cells P2 8 I/O Cell P3 8 I/O Cells 3.5–3.7 available on C8051F360 interface, a full-duplex UART with enhanced baud rate Rev. 1.0 P0.0 P0.7 P1.0 P1.7 P2.0 P2.7 3.1–3.4 available on P3.0 C8051F360/1/3/4/6/8 P3.7 ...
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... Analog to Digital Converter The C8051F360/1/2/6/7/8/9 devices include an on-chip 10-bit SAR ADC with channels for the dif- ferential input multiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL and DNL of ±1 LSB. The ADC system includes a configurable analog multiplexer that selects both positive and negative ADC inputs. Ports1-3 are available as an ADC inputs ...
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... Figure 1.12 shows the Comparator0 block diagram, and Figure 1.13 shows the Comparator1 block dia- gram. Note: The first Port I/O pins shown in Figure 1.12 and Figure 1.13 are for the 48-pin (C8051F360/3) devices. The second set of Port I/O pins are for the 32-pin and 28-pin (C8051F361/2/4/5/6/7/8/9) devices. ...
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... CMX0N2 CP0HYP1 CMX0N1 CP0HYP0 CMX0N0 CP0HYN1 CP0HYN0 CMX0P1 CMX0P0 P1.4 / P1.0 P2.3 / P1.4 P3.1 / P2.0 P3.5 / P2.4 P1.5 / P1.1 P2.4 / P1.5 P3.2 / P2.1 P3.6 / P2.5 Figure 1.12. Comparator0 Block Diagram C8051F360/1/2/3/4/5/6/7/8/9 VDD CP0 + + SET SET CLR CLR (SYNCHRONIZER) GND Reset Decision ...
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... Current Output DAC The C8051F360/1/2/6/7/8/9 devices includes a 10-bit current-mode Digital-to-Analog Converter (IDA0). The maximum current output of the IDA0 can be adjusted for three different current settings; 0.5 mA, 1 mA, and 2 mA. IDA0 features a flexible output update mechanism which allows for seamless full-scale changes and supports jitter-free updates for waveform generation ...
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... IDA0EN IDA0CM2 IDA0CM1 IDA0CM0 IDA0OMD1 IDA0OMD0 8 2 Figure 1.14. IDA0 Functional Block Diagram C8051F360/1/2/3/4/5/6/7/8/9 10 IDA0 Rev. 1.0 IDA0 31 ...
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... C8051F360/1/2/3/4/5/6/7/8/9 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on any Port I/O Pin or RST with respect to GND Voltage on V with respect to GND DD Maximum Total current through V DD Maximum output current sunk by RST or any Port pin Note: Stresses above those listed under “ ...
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... MHz 3 kHz MHz I Supply Sensitivity MHz 3 3 <= 20 MHz Frequency Sensitivity 3 > 20 MHz 3 <= 20 MHz 3 > 20 MHz C8051F360/1/2/3/4/5/6/7/8/9 Conditions Min 2.7 3.0 — –40 — — — — — — — — C — ° C — ° C — ° C — ° ...
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... C8051F360/1/2/3/4/5/6/7/8/9 Table 3.1. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash 3 100 MHz 3 MHz 3 100 MHz 3 MHz 3 MHz 3 kHz MHz 3 I Supply Sensitivity ...
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... IDAC Electrical Characteristics Voltage Reference Electrical Characteristics Comparator Electrical Characteristics Reset Electrical Characteristics Flash Electrical Characteristics Internal High Frequency Oscillator Electrical Characteristics Internal Low Frequency Oscillator Electrical Characteristics PLL Frequency Characteristics Port I/O DC Electrical Characteristics C8051F360/1/2/3/4/5/6/7/8/9 Rev. 1.0 Page No 134 144 ...
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... C8051F360/1/2/3/4/5/6/7/8/9 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F36x Pin Pin Pin Name ‘F360/3 ‘F361/4/6/8 ‘F362/5/7/9 (48-pin) (32-pin) (28-pin) V 19, 31 GND 18, 30 AGND 6 — AV+ 7 — RST C2CK P4.6/ 9 — C2D P3.0/ — 6 C2D P0.6 ...
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... P3.0 25 — — C8051F360/1/2/3/4/5/6/7/8/9 Type Description D I/O or Port 1.0. See Section 17 for a complete description I/O or Port 1.1. See Section 17 for a complete description I/O or Port 1.2. See Section 17 for a complete description I/O or Port 1.3. See Section 17 for a complete description I/O or Port 1.4. See Section 17 for a complete description. ...
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... C8051F360/1/2/3/4/5/6/7/8/9 Table 4.1. Pin Definitions for the C8051F36x (Continued) Pin Pin Pin Name ‘F360/3 ‘F361/4/6/8 ‘F362/5/7/9 (48-pin) (32-pin) (28-pin P3.5 20 — P3.6 17 — P3.7 16 — P4.0 15 — P4.1 14 — P4.2 13 — P4.3 12 — P4.4 11 — P4.5 10 — 38 Type — ...
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... P0.4 1 P0.3 2 P0.2 3 P0.1 4 P0.0 5 AGND 6 AV+ 7 /RST/C2CK 8 P4.6/C2D 9 P4.5 10 P4.4 11 P4.3 12 Figure 4.1. TQFP-48 Pinout Diagram (Top View) C8051F360/1/2/3/4/5/6/7/8/9 C8051F360/3 Rev. 1.0 P1.7 36 P2.0 35 P2 P2.3 31 VDD GND 30 P2.4 29 P2.5 28 P2.6 27 P2 ...
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... C8051F360/1/2/3/4/5/6/7/8/9 Figure 4.2. TQFP-48 Package Diagram Table 4.2. TQFP-48 Package Dimensions Dimension Min Nom A — — A1 0.05 — A2 0.95 1.00 b 0.17 0.22 c 0.09 — D 9.00 BSC. D1 7.00 BSC. e 0.50 BSC. Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. ...
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... P0 P0.0 GND 3 VDD 4 C8051F361/4/6/8 5 /RST/C2CK 6 P3.0/C2D 7 P3.1 8 P3.2 Figure 4.3. LQFP-32 Pinout Diagram (Top View) C8051F360/1/2/3/4/5/6/7/8/9 Rev. 1.0 24 P1.2 23 P1.3 22 P1.4 21 P1.5 20 P1.6 19 P1.7 18 P2.0 17 P2.1 41 ...
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... C8051F360/1/2/3/4/5/6/7/8/9 Figure 4.4. LQFP-32 Package Diagram Table 4.3. LQFP-32 Package Dimensions Dimension Min Nom A — — A1 0.05 — A2 1.35 1.40 b 0.30 0.37 c 0.09 — D 9.00 BSC. D1 7.00 BSC. e 0.80 BSC. Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. ...
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... P0.1 1 P0.0 2 GND 3 C8051F362/5/7/9 VDD 4 /RST/C2CK 5 6 P3.0/C2D P2.7 7 Figure 4.5. QFN-28 Pinout Diagram (Top View) C8051F360/1/2/3/4/5/6/7/8/9 GND Rev. 1.0 21 P1.1 20 P1.2 19 P1.3 18 P1.4 17 P1.5 16 P1.6 15 P1.7 43 ...
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... C8051F360/1/2/3/4/5/6/7/8/9 Figure 4.6. QFN-28 Package Drawing Table 4.4. QFN-28 Package Dimensions Dimension Min Nom A 0.80 0.90 A1 0.03 0.07 A3 0.25 REF b 0.18 0.25 D 5.00 BSC. D2 2.90 3.15 e 0.50 BSC. E 5.00 BSC. Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. ...
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... C8051F360/1/2/3/4/5/6/7/8/9 Figure 4.7. Typical QFN-28 Landing Diagram Rev. 1.0 45 ...
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... C8051F360/1/2/3/4/5/6/7/8/9 Figure 4.8. QFN-28 Solder Paste Recommendation 46 Rev. 1.0 ...
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... ADC (ADC0, C8051F360/1/2/6/7/8/9) The ADC0 subsystem for the C8051F360/1/2/6/7/8/9 consists of two analog multiplexers (referred to col- lectively as AMUX0) with 23 total input selections, and a 200 ksps, 10-bit successive-approximation-regis- ter ADC with integrated track-and-hold and programmable window detector. The AMUX0, data conversion modes, and window detector are all configurable under software control via the Special Function Registers shown in Figure 5 ...
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... C8051F360/1/2/3/4/5/6/7/8/9 5.1. Analog Multiplexer AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the positive input: the AMUX0 Port I/O inputs, the on-chip temperature sensor, or the positive power supply (V ). Any of the following may be selected as the negative input: the AMUX0 Port I/O inputs, VREF GND. When GND is selected as the negative input, ADC0 operates in Single-ended Mode ...
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... Figure 5.3 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Note that parameters which affect ADC measurement, in particular the voltage reference value, will also affect temperature measurement. C8051F360/1/2/3/4/5/6/7/8 Slope*(TEMP ) + ...
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... C8051F360/1/2/3/4/5/6/7/8/9 5.00 4.00 3.00 2.00 1.00 0.00 -40.00 -20.00 -1.00 -2.00 -3.00 -4.00 -5.00 Figure 5.3. Temperature Sensor Error with 1-Point Calibration 50 40.00 0.00 20.00 Temperature (degrees C) Rev. 1.0 5.00 4.00 3.00 2.00 1.00 0.00 60.00 80.00 -1.00 -2.00 -3.00 -4.00 ...
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... Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.7 on the C8051F360 devices and Port pin P0.6 on the C8051F361/2/6/7/8/9 devices. When the CNVSTR input is used as the ADC0 conversion source, the corresponding port pin should be skipped by the Digital Cross- bar. To configure the Crossbar to skip the port pin, set the appropriate bit to ‘ ...
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... C8051F360/1/2/3/4/5/6/7/8/9 5.3.2. Tracking Modes According to Table 5.1, each ADC0 conversion must be preceded by a minimum tracking time for the con- verted result to be accurate. The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic ‘ ...
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... ADC resolution in bits (10). Differential Mode MUX Select Px MUX Input MUX SAMPLE Px MUX MUX Select Figure 5.5. ADC0 Equivalent Input Circuits C8051F360/1/2/3/4/5/6/7/8/9 reduces See Table 5.1 for ADC0 minimum TOTAL MUX n ⎛ ⎞ 2 × ------ - ⎝ ⎠ TOTAL SAMPLE SA Single-Ended Mode MUX Select Px ...
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... Notes: 1. Only applies to C8051F361/2/6/7/8/9 (32-pin and 28-pin); selection RESERVED on C8051F360 (48-pin) device. 2. Only applies to C8051F360/1/6/8 (48-pin and 32-pin); selection RESERVED on C8051F362/7/9 (28-pin) devices. 54 R/W R/W R/W AMX0P4 AMX0P3 AMX0P2 AMX0P1 Bit4 Bit3 Bit2 ...
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... Notes: 1. Only applies to C8051F361/2/6/7/8/9 (32-pin and 28-pin); selection RESERVED on C8051F360 (48-pin) device. 2. Only applies to C8051F360/1/6/8 (48-pin and 32-pin); selection RESERVED on C8051F362/7/9 (28-pin) devices. C8051F360/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 ADC0 Negative Input (1) P1 ...
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... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 5.3. ADC0CF: ADC0 Configuration SFR Page: all pages SFR Address: 0xBC R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits 7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC4– ...
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... Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conversion. 100: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR edge. 101: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conversion. 11x: Reserved . C8051F360/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W ...
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... C8051F360/1/2/3/4/5/6/7/8/9 5.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times ...
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... SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte SFR Page: all pages SFR Address: 0xC5 R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: Low byte of ADC0 Less-Than Data Word. C8051F360/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W R/W ...
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... C8051F360/1/2/3/4/5/6/7/8/9 5.4.1. Window Detector In Single-Ended Mode Figure 5.6 shows two example window comparisons for right-justified, single-ended data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer value ...
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... ADC0LTH:ADC0LTL 0x0FC0 0x0000 VREF x (-1/512) 0xFFC0 ADC0GTH:ADC0GTL 0xFF80 AD0WINT not affected 0x8000 -VREF Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data C8051F360/1/2/3/4/5/6/7/8/9 ADC0H:ADC0L Input Voltage (Px.x - Px.x) VREF x (511/512) 0x01FF 0x0041 VREF x (64/512) 0x0040 0x003F AD0WINT=1 0x0000 VREF x (-1/512) ...
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... C8051F360/1/2/3/4/5/6/7/8/9 Table 5.1. ADC0 Electrical Characteristics V = 3.0 V, VREF = 2.40 V (REFSL=0), –40 to +85 °C unless otherwise specified. DD Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Dynamic Performance (10 kHz sine-wave Single-ended input below Full Scale, 200 ksps) Signal-to-Noise Plus Distortion ...
Page 63
... The IDAC is enabled or disabled with the IDA0EN bit in the IDA0 Control Register (see SFR Definition 6.1). When IDA0EN is set to ‘0’, the IDAC port pin (P0.4 for C8051F360, P0.1 for C8051F361/2/6/7/8/9) behaves as a normal GPIO pin. When IDA0EN is set to ‘1’, the digital output drivers and weak pullup for the IDAC pin are automatically disabled, and the pin is connected to the IDAC output ...
Page 64
... C8051F360/1/2/3/4/5/6/7/8/9 6.1.2. Update Output Based on Timer Overflow Similar to the ADC operation, in which an ADC conversion can be initiated by a timer overflow indepen- dently of the processor, the IDAC outputs can use a Timer overflow to schedule an output update event. This feature is useful in systems where the IDAC is used to generate a waveform of a defined sampling rate by eliminating the effects of variable interrupt latency and instruction execution on the timing of the IDAC output. When the IDA0CM bits (IDA0CN.[6:4]) are set to ‘ ...
Page 65
... SFR Page: all pages SFR Address: 0x97 R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: IDA0 Data Word High-Order Bits. Bits 7–0 are the most-significant bits of the 10-bit IDA0 Data Word. C8051F360/1/2/3/4/5/6/7/8/9 R R/W – – Bit4 Bit3 Bit2 Bit1 R/W R/W ...
Page 66
... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 6.3. IDA0L: IDA0 Data Word LSB SFR Page: all pages SFR Address: 0x96 R/W R/W R — Bit7 Bit6 Bit5 Bits 7–6: IDA0 Data Word Low-Order Bits. Lower 2 bits of the 10-bit Data Word. Bits 5–0: UNUSED. Read = 000000b, Write = don’t care. ...
Page 67
... REFBE bit should be cleared to ‘0’. Electrical specifications for the internal voltage reference are given in Table 7.1. Important Note about the VREF Pin: Port pin P0.3 on the C8051F360 device and P0.0 on C8051F361/2/6/7/89 devices is used as the external VREF input and as an output for the internal VREF. ...
Page 68
... C8051F360/1/2/3/4/5/6/7/8/9 complete Port I/O configuration details. The TEMPE bit in register REF0CN enables/disables the tempera- ture sensor. While disabled, the temperature sensor defaults to a high impedance state and any ADC0 measurements performed on the sensor result in meaningless data. SFR Definition 7.1. REF0CN: Reference Control ...
Page 69
... Input Current 3.0 V BIASE = ‘1’ or AD0EN = ‘1’ or ADC Bias Generator IOSCEN = ‘1’ REFBE = ‘1’ or TEMPE = ‘1’ or Reference Bias Generator IDA0EN = ‘1’ C8051F360/1/2/3/4/5/6/7/8/9 Conditions Min Internal Reference (REFBE = 1) 2.35 External Reference (REFBE = 0) Power Specifications Rev. 1.0 ...
Page 70
... C8051F36x devices include two on-chip programmable voltage comparators, Comparator0 and Comparator1, shown in Figure 8.1 and Figure 8.2 (Note: the port pin Comparator inputs differ between C8051F36x devices. The first Port I/O pin shown is for C8051F360/3 devices). The comparators offer programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “ ...
Page 71
... The Comparator response time may be configured in software via the CPT0MD and CPT1MD registers (see SFR Definition 8.3 and SFR Definition 8.6). Selecting a longer response time reduces the Comparator supply current. See Table 8.1 for complete timing and power consumption specifications. C8051F360/1/2/3/4/5/6/7/8/9 CP1EN CP1RIF ...
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... C8051F360/1/2/3/4/5/6/7/8/9 CP0+ VIN+ + CP0 CP0- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS VIN OUTPUT V OL Positive Hysteresis Disabled Figure 8.3. Comparator Hysteresis Plot The Comparator hysteresis is software-programmable via the Comparator Control registers CPT0CN and CPT1CN. The user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hysteresis around the threshold voltage. The Comparator hysteresis is programmed using Bits3– ...
Page 73
... Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. Bits 1–0: CP0HYN1–0: Comparator0 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. C8051F360/1/2/3/4/5/6/7/8/9 R/W R/W R/W CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000 Bit4 Bit3 Bit2 Rev ...
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... CMX0P1 CMX0P0 Bit4 Bit3 Bit2 Bit1 C8051F360/3 C8051F361/2/4/5/6/7/8/9 Negative Input Negative Input P1.5 P1.1 P2.4 P1.5 P3.2 P2.1 P3.6 P2.5 C8051F360/3 C8051F361/2/4/5/6/7/8/9 Positive Input Positive Input P1.4 P1.0 P2.3 P1.4 P3.1 P2.0 P3.5 P2.4 Rev. 1.0 R/W Reset Value 11111111 Bit0 ...
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... Bits 3–2: UNUSED. Read = 00b, Write = don’t care. Bits 1–0: CP0MD1–CP0MD0: Comparator0 Mode Select These bits select the response time for Comparator0. Mode CP0MD1 CP0MD0 C8051F360/1/2/3/4/5/6/7/8/9 R R/W – – CP0MD1 CP0MD0 00000010 Bit4 Bit3 Bit2 Bit1 CP0 Response Time (TYP) 0 ...
Page 76
... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 8.4. CPT1CN: Comparator1 Control SFR Page: all pages SFR Address: 0x9A R/W R R/W CP1EN CP1OUT CP1RIF Bit7 Bit6 Bit5 Bit 7: CP1EN: Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. Bit 6: CP1OUT: Comparator1 Output State Flag. 0: Voltage on CP1+ < CP1–. ...
Page 77
... CMX1P1 CMX1P0 Bit4 Bit3 Bit2 C8051F360/3 C8051F361/2/4/5/6/7/8/9 Negative Input Negative Input P2.1 P1.3 P2.6 P1.7 P3.4 P2.3 P4.0 P2.7 C8051F360/3 C8051F361/2/4/5/6/7/8/9 Positive Input Positive Input P2.0 P1.2 P2.5 P1.6 P3.3 P2.2 P3.7 P2.6 Rev. 1.0 R/W R/W Reset Value 11111111 ...
Page 78
... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 8.6. CPT1MD: Comparator1 Mode Selection SFR Page: all pages SFR Address: 0x9C R R R/W – – CP1RIE Bit7 Bit6 Bit5 Bits 7–6: UNUSED. Read = 00b, Write = don’t care. Bit 5: CP1RIE: Comparator1 Rising-Edge Interrupt Enable. 0: Comparator1 Rising-edge interrupt disabled. ...
Page 79
... Input Bias Current Input Offset Voltage Power Supply Power Supply Rejection Power-up Time Mode 0 Mode 1 Supply Current at DC Mode 2 Mode 3 *Note: Vcm is the common-mode voltage on CPx+ and CPx–. C8051F360/1/2/3/4/5/6/7/8/9 Conditions Min Typ — 100 — 250 — 175 — 500 — ...
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... C8051F360/1/2/3/4/5/6/7/8/9 9. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are ...
Page 81
... The IDE's debugger and programmer interface to the CIP-51 via its C2 interface to provide fast and efficient in-system device programming and debugging. Third party macro assemblers and C compil- ers are also available. C8051F360/1/2/3/4/5/6/7/8/9 DATA BUS B REGISTER TMP1 ...
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... C8051F360/1/2/3/4/5/6/7/8/9 9.3. Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc- tion set; standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes, addressing modes and effect on PSW flags ...
Page 83
... MOV Rn, direct Move direct byte to Register MOV Rn, #data Move immediate to Register MOV direct, A Move A to direct byte MOV direct, Rn Move Register to direct byte MOV direct, direct Move direct byte to direct byte C8051F360/1/2/3/4/5/6/7/8/9 Logical Operations Data Transfer Rev. 1.0 Clock Bytes Cycles ...
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... C8051F360/1/2/3/4/5/6/7/8/9 Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description MOV direct, @Ri Move indirect RAM to direct byte MOV direct, #data Move immediate to direct byte MOV @Ri, A Move A to indirect RAM MOV @Ri, direct Move direct byte to indirect RAM MOV @Ri, #data Move immediate to indirect RAM ...
Page 85
... LCALL and LJMP. The destination may be anywhere within the 64K-byte program memory space. There is one unused opcode (0xA5) that performs the same function as NOP. All mnemonics copyrighted © Intel Corporation 1980. C8051F360/1/2/3/4/5/6/7/8/9 Rev. 1.0 Clock Bytes ...
Page 86
... Byte Sectors) 0x0000 9.4.1. Program Memory The CIP-51 core has program memory space. The C8051F360/1/2/3/4/5/6/7 implement this program memory space as in-system, re-programmable Flash memory, organized in a contiguous block from addresses 0x0000 to 0x7BFF. Addresses above 0x7BFF are reserved on the 32 kB devices. The C8051F368/9 implement Flash from addresses 0x0000 to 0x3FFF. ...
Page 87
... The stack depth can extend up to 256 bytes. The MCUs also have built-in hardware for a stack record which is accessed by the debug logic. The stack record is a 32-bit shift register, where each PUSH or increment SP pushes one record bit onto the register, C8051F360/1/2/3/4/5/6/7/8/9 Rev. 1.0 87 ...
Page 88
... C8051F360/1/2/3/4/5/6/7/8/9 and each CALL pushes two record bits onto the register. (A POP or decrement SP pops one record bit, and a RET pops two record bits, also.) The stack record circuitry can also detect an overflow or underflow on the 32-bit shift register, and can notify the debug software even with the MCU running at speed. ...
Page 89
... SFR resides. Note that certain SFR’s are accessible from ALL SFR pages, and are denoted by the back- ground shading in the table. For example, the Port I/O registers P0, P1, P2, and P3 all have a shaded background, indicating these SFR’s are accessible from all SFR pages regardless of the SFRPAGE regis- ter value. C8051F360/1/2/3/4/5/6/7/8/9 SFRPGCN Bit SFRPAGE SFRNEXT SFRLAST Rev ...
Page 90
... C8051F360/1/2/3/4/5/6/7/8/9 9.4.6.3. SFR Page Stack Example The following is an example that shows the operation of the SFR Page Stack during interrupts. In this example, the SFR Page Control is left in the default enabled state (i.e., SFRPGEN = 1), and the CIP-51 is executing in-line code that is writing values to OSCICN (SFR “OSCICN”, located at address 0xB6 on SFR Page 0x0F) ...
Page 91
... Note that a value stored in SFRLAST (via a previous software write to the SFRLAST register) will be overwritten. See Figure 9.6 below. SFRPAGE pushed to SFRNEXT SFRNEXT pushed to SFRLAST Figure 9.6. SFR Page Stack Upon PCA Interrupt Occurring During an ADC0 ISR C8051F360/1/2/3/4/5/6/7/8/9 SFR Page 0x00 Automatically pushed on stack in SFRPAGE on ADC0 interrupt 0x00 SFRPAGE (ADC0) ...
Page 92
... C8051F360/1/2/3/4/5/6/7/8/9 On exit from the PCA interrupt service routine, the CIP-51 will return to the ADC0 Window Comparator ISR. On execution of the RETI instruction, SFR Page 0x00 used to access the PCA registers will be auto- matically popped off of the SFR Page Stack, and the contents of the SFRNEXT register will be moved to the SFRPAGE register. Software in the ADC0 ISR can continue to access SFR’ ...
Page 93
... RETI instruction). The automatic switching of the SFRPAGE and operation of the SFR Page Stack as described above can be disabled in software by clearing the SFR Automatic Page Enable Bit (SFRPGEN) in the SFR Page Control Register (SFR0CN). See SFR Definition 9.1. C8051F360/1/2/3/4/5/6/7/8/9 SFR Page 0x00 Automatically ...
Page 94
... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 9.1. SFR0CN: SFR Page Control SFR Page: F SFR Address: 0xE5 R/W R/W R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved SFRPGEN 00000001 Bit7 Bit6 Bit5 Bits 7–1: RESERVED. Read = 0000000b. Must Write 0000000b. Bit 0: SFRPGEN: SFR Automatic Page Control Enable. ...
Page 95
... Write: Sets the SFR Page in the last entry of the SFR Stack. This will cause the SFRNEXT SFR to have this SFR page value upon a return from interrupt. Read: Returns the value of the SFR page contained in the last entry of the SFR stack. C8051F360/1/2/3/4/5/6/7/8/9 R/W R/W ...
Page 96
... C8051F360/1/2/3/4/5/6/7/8/9 Table 9.2. Special Function Register (SFR) Memory Map 0(8) 1( SPI0CN PCA0L MAC0BL F P0MDIN E8 0 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 ACC P1MAT F XBR0 D8 0 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 PCA0CPM5 PSW REF0CN MAC0ACC0 TMR2CN - F CCH0TN C0 0 SMB0CN ...
Page 97
... EIE2 0xE7 All Pages Extended Interrupt Enable 2 EIP1 0xCE F EIP2 0xCF F Notes: 1. Refers to a register in the C8051F360/1/2/6/7/8/9 only. 2. Refers to a register in the C8051F360/3 only. C8051F360/1/2/3/4/5/6/7/8/9 Description Cache Control Cache Lock Cache Miss Accumulator Cache Tuning System Clock Select Extended Interrupt Priority 1 Extended Interrupt Priority 2 Rev ...
Page 98
... F P0 0x80 All Pages Port 0 Latch P0MASK 0xF4 0 Notes: 1. Refers to a register in the C8051F360/1/2/6/7/8/9 only. 2. Refers to a register in the C8051F360/3 only. 98 Description EMIF Configuration EMIF Timing Control Flash Lock and Key Flash Scale Flash Status MAC0 Accumulator Byte 0 (LSB) MAC0 Accumulator Byte 1 ...
Page 99
... All Pages PCA Module 0 Capture/Compare Low Byte PCA0CPL1 0xE9 All Pages PCA Module 1 Capture/Compare Low Byte Notes: 1. Refers to a register in the C8051F360/1/2/6/7/8/9 only. 2. Refers to a register in the C8051F360/3 only. C8051F360/1/2/3/4/5/6/7/8/9 Description Port 0 Match Port 0 Input Mode Port 0 Output Mode Configuration ...
Page 100
... SMB0CN 0xC0 All Pages SMBus Control SMB0DAT 0xC2 All Pages SMBus Data Notes: 1. Refers to a register in the C8051F360/1/2/6/7/8/9 only. 2. Refers to a register in the C8051F360/3 only. 100 Description PLL Control PLL Divider PLL Filter PLL Multiplier Flash Write/Erase Control SFR Page Control Rev ...
Page 101
... All Pages Timer 3 Reload Register Low Byte VDM0CN 0xFF All Pages V XBR0 0xE1 F XBR1 0xE2 F Notes: 1. Refers to a register in the C8051F360/1/2/6/7/8/9 only. 2. Refers to a register in the C8051F360/3 only. C8051F360/1/2/3/4/5/6/7/8/9 Description Monitor Control DD Port I/O Crossbar Control 0 Port I/O Crossbar Control 1 Rev. 1.0 Page No. page 102 ...
Page 102
... C8051F360/1/2/3/4/5/6/7/8/9 9.4.7. Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic ‘1’. Future product versions may use these bits to implement new features in which case the reset value of the bit will be logic ‘0’, selecting the feature's default state. Detailed descrip- tions of the remaining SFRs are included in the sections of the data sheet associated with their corre- sponding system function ...
Page 103
... Bit 1: F1: User Flag 1. This is a bit-addressable, general purpose flag for use under software control. Bit 0: PARITY: Parity Flag. This bit is set the sum of the eight bits in the accumulator is odd and cleared if the sum is even. C8051F360/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W RS1 RS0 ...
Page 104
... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 9.9. ACC: Accumulator SFR Page: all pages (bit addressable) SFR Address: 0xE0 R/W R/W R/W ACC.7 ACC.6 ACC.5 Bit7 Bit6 Bit5 Bits 7–0: ACC: Accumulator. This register is the accumulator for arithmetic operations. SFR Definition 9.10 Register SFR Page: ...
Page 105
... Suspend Mode The C8051F36x devices feature a low-power SUSPEND mode, which stops the internal oscillator until an awakening event occurs. See Section “16.1.1. Internal Oscillator Suspend Mode” on page 170. C8051F360/1/2/3/4/5/6/7/8/9 All internal registers and memory maintain their original Rev. 1.0 105 ...
Page 106
... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 9.11. PCON: Power Control SFR Page: all pages SFR Address: 0x87 R/W R/W R/W Reserved Reserved Reserved Reserved Reserved Reserved Bit7 Bit6 Bit5 Bits 7–3: RESERVED. Read = 000000b. Must Write 000000b. Bit 1: STOP: STOP Mode Select. Writing a ‘1’ to this bit will place the CIP-51 into STOP mode. This bit will always read ‘0’. ...
Page 107
... Table 10.1 on page 108. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). C8051F360/1/2/3/4/5/6/7/8/9 Rev. 1.0 107 ...
Page 108
... C8051F360/1/2/3/4/5/6/7/8/9 10.2. Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior- ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP, EIP1, or EIP2) used to configure its priority level ...
Page 109
... The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). C8051F360/1/2/3/4/5/6/7/8/9 Priority Pending Flag Order CF (PCA0CN ...
Page 110
... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 10.1. IE: Interrupt Enable SFR Page: all pages (bit addressable) SFR Address: 0xA8 R/W R/W R/W EA ESPI0 ET2 Bit7 Bit6 Bit5 Bit 7: EA: Global Interrupt Enable. This bit globally enables/disables all interrupts. It overrides the individual interrupt mask set- tings. ...
Page 111
... Timer 0 interrupt set to low priority level. 1: Timer 0 interrupt set to high priority level. Bit 0: PX0: External Interrupt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupt. 0: External Interrupt 0 set to low priority level. 1: External Interrupt 0 set to high priority level. C8051F360/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W PS0 PT1 ...
Page 112
... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 10.3. EIE1: Extended Interrupt Enable 1 SFR Page: all pages SFR Address: 0xE6 R/W R/W R/W ET3 ECP1 ECP0 Bit7 Bit6 Bit5 Bit 7: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3L or TF3H flags. ...
Page 113
... Bit 1: UNUSED. Read = 0b. Write = don’t care. Bit 0: PSMB0: SMBus (SMB0) Interrupt Priority Control. This bit sets the priority of the SMB0 interrupt. 0: SMB0 interrupt set to low priority level. 1: SMB0 interrupt set to high priority level. C8051F360/1/2/3/4/5/6/7/8/9 R/W R/W R/W PPCA0 PADC0 PWADC0 ...
Page 114
... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 10.5. EIE2: Extended Interrupt Enable 2 SFR Page: all pages SFR Address: 0xE7 R/W R/W R/W – – – Bit7 Bit6 Bit5 Bits 7–2: UNUSED. Read = 000000b. Write = don’t care. Bit 1: EMAT: Enable Port Match Interrupt. This bit sets the masking of the Port Match interrupt. ...
Page 115
... IN1PL); the flag remains logic ‘0’ while the input is inac- tive. The external interrupt source must hold the input active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated. C8051F360/1/2/3/4/5/6/7/8/9 IT1 IN1PL 1 ...
Page 116
... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 10.7. IT01CF: INT0/INT1 Configuration SFR Page: all pages SFR Address: 0xE4 R/W R/W R/W IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 Note: Refer to SFR Definition 21.1. “TCON: Timer Control” on page 252 for INT0/1 edge- or level-sensitive interrupt selection. Bit 7: IN1PL: /INT1 Polarity 0: /INT1 input is active low ...
Page 117
... The MAC0 Accumulator register is 40 bits long, and consists of five SFRs: MAC0OVR, MAC0ACC3, MAC0ACC2, MAC0ACC1, and MAC0ACC0. The primary results of a MAC0 operation are stored in the Accumulator registers. If they are needed, the rounded results (MAC0RNDH:MAC0RNDL). C8051F360/1/2/3/4/5/6/7/8/9 MAC0 B Register MAC0AL MAC0BH MAC0BL MAC0MS Multiply 1 ...
Page 118
... C8051F360/1/2/3/4/5/6/7/8/9 11.2. Integer and Fractional Math MAC0 is capable of interpreting the 16-bit inputs stored in MAC0A and MAC0B as signed integers or as signed fractional numbers. When the MAC0FM bit (MAC0CF.1) is cleared to ‘0’, the inputs are treated as 16-bit, 2’s complement, integer values. After the operation, the accumulator will contain a 40-bit, 2’s com- plement, integer value ...
Page 119
... When the MAC0SD bit is set to ‘1’, the MAC0 accumulator will shift right. Right-shift operations are sign-extended with the current value of bit 39. Note that the status flags in the MAC0STA register are not affected by shift operations. C8051F360/1/2/3/4/5/6/7/8/9 Accumulator Rounded Results Results Available ...
Page 120
... C8051F360/1/2/3/4/5/6/7/8/9 11.6. Rounding and Saturation A Rounding Engine is included, which can be used to provide a rounded result when operating on frac- tional numbers. MAC0 uses an unbiased rounding algorithm to round the data stored in bits 31–16 of the accumulator, as shown in Table 11.1. Rounding occurs during the third stage of the MAC0 pipeline, after any shift operation write to the LSB of the accumulator ...
Page 121
... The rounding register is updated after this instruction MOV MAC0CF, #30h ; Initiate a Right-shift MOV MAC0CF, #30h ; Initiate a second Right-shift NOP ; After this instruction, the accumulator should be 0xE044221108 NOP ; The rounding register is updated after this instruction C8051F360/1/2/3/4/5/6/7/8/9 × 4660 – 292 = – 1360720 Rev. 1.0 121 ...
Page 122
... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 11.1. MAC0CF: MAC0 Configuration SFR Page: 0 SFR Address: 0xD7 R R R/W – – MAC0SC MAC0SD MAC0CA MAC0SAT MAC0FM MAC0MS 00000000 Bit7 Bit6 Bit5 Bits 7–6: UNUSED: Read = 00b, Write = don’t care. Bit 5: MAC0SC: Accumulator Shift Control. When set to 1, the 40-bit MAC0 Accumulator register will be shifted during the next SYSCLK cycle. The direction of the shift (left or right) is controlled by the MAC0SD bit. This bit is cleared to ‘ ...
Page 123
... The contents of this register should not be changed by software during the first two MAC0 pipeline stages. SFR Definition 11.3. MAC0AH: MAC0 A High Byte SFR Page: 0 SFR Address: 0xA5 Bit7 Bit6 Bit5 Bits 7–0: High Byte (bits 15–8) of MAC0 A Register. C8051F360/1/2/3/4/5/6/7/8/9 R R/W R/W R/W – MAC0HO MAC0Z MAC0SO Bit4 Bit3 Bit2 Bit1 R ...
Page 124
... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 11.4. MAC0AL: MAC0 A Low Byte SFR Page: 0 SFR Address: 0xA4 Bit7 Bit6 Bit5 Bits 7–0: Low Byte (bits 7–0) of MAC0 A Register. SFR Definition 11.5. MAC0BH: MAC0 B High Byte SFR Page: 0 SFR Address: 0xF2 Bit7 Bit6 Bit5 Bits 7–0: High Byte (bits 15–8) of MAC0 B Register. ...
Page 125
... SFR Definition 11.9. MAC0ACC1: MAC0 Accumulator Byte 1 SFR Page: 0 SFR Address: 0xD3 Bit7 Bit6 Bit5 Bits 7–0: Byte 1 (bits 15–8) of MAC0 Accumulator. Note:The contents of this register should not be changed by software during the first two MAC0 pipeline stages. C8051F360/1/2/3/4/5/6/7/8 Bit4 Bit3 Bit2 Bit1 ...
Page 126
... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 11.10. MAC0ACC0: MAC0 Accumulator Byte 0 SFR Page: 0 SFR Address: 0xD2 Bit7 Bit6 Bit5 Bits 7–0: Byte 0 (bits 7–0) of MAC0 Accumulator. Note:The contents of this register should not be changed by software during the first two MAC0 pipeline stages. SFR Definition 11.11. MAC0OVR: MAC0 Accumulator Overflow ...
Page 127
... SFR Definition 11.13. MAC0RNDL: MAC0 Rounding Register Low Byte SFR Page: 0 SFR Address: 0xAE Bit7 Bit6 Bit5 Bits 7–0: Low Byte (bits 7–0) of MAC0 Rounding Register. C8051F360/1/2/3/4/5/6/7/8 Bit4 Bit3 Bit2 Bit1 Rev. 1.0 R Reset Value 00000000 Bit0 127 ...
Page 128
... C8051F360/1/2/3/4/5/6/7/8/9 12. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution • Special Function Registers (SFRs) are initialized to their defined reset values • External Port pins are forced to a known state • ...
Page 129
... PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem- ory should be assumed to be undefined after a power-on reset. The V power-on reset. 2.70 V RST 2.55 2.0 1.0 /RST Logic HIGH Logic LOW Figure 12.2. Power-On and V C8051F360/1/2/3/4/5/6/7/8/9 ramps from PORDelay VDD Power-On Monitor Reset Reset Monitor Reset Timing DD Rev ...
Page 130
... C8051F360/1/2/3/4/5/6/7/8/9 12.2. Power-Fail Reset/V DD When a power-down transition or power irregularity causes V monitor will drive the RST pin low and hold the CIP- reset state (see Figure 12.2). When level above V , the CIP-51 will be released from the reset state. Note that even though internal data ...
Page 131
... CP0+) is less than the inverting input voltage (on CP0-), the device is put into the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read ‘1’ signifying Comparator0 as the reset source; otherwise, this bit reads ‘0’. The state of the RST pin is unaffected by this reset. C8051F360/1/2/3/4/5/6/7/8/9 Monitor Control DD R ...
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... C8051F360/1/2/3/4/5/6/7/8/9 12.6. PCA Watchdog Timer Reset The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be used to prevent software from running out of control during a system malfunction. The PCA WDT function can be enabled or disabled by software as described in Section “22.3. Watchdog Timer Mode” on page 272 ...
Page 133
... Read: Last reset was not a power- reset source. 1: Read: Last reset was a power- indeterminate. Write: V Bit 0: PINRSF: HW Pin Reset Flag. 0: Source of last reset was not RST pin. 1: Source of last reset was RST pin. C8051F360/1/2/3/4/5/6/7/8/9 R/W R R/W WDTRSF MCDRSF PORSF Bit4 Bit3 Bit2 Monitor reset ...
Page 134
... C8051F360/1/2/3/4/5/6/7/8/9 Table 12.1. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter I OL RST Output Low Voltage V DD RST Input High Voltage RST Input Low Voltage RST Input Pullup Impedance V POR Threshold ( RST Missing Clock Detector Time- Time from last system clock ...
Page 135
... Flash Memory All devices include either 32 kB (C8051F360/1/2/3/4/5/6/ (C8051F368/9) of on-chip, reprogram- mable Flash memory for program code or non-volatile data storage. The Flash memory can be pro- grammed in-system through the C2 interface software using the MOVX write instructions. Once cleared to logic ‘0’, a Flash bit must be erased to set it back to logic ‘1’. Bytes should be erased (set to 0xFF) before being reprogrammed. Flash write and erase operations are automatically timed by hardware for proper execution. During a Flash erase or write, the FLBUSY bit in the FLSTAT register is set to ‘ ...
Page 136
... C8051F360/1/2/3/4/5/6/7/8/9 erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a Flash write or erase is attempted before the key codes have been written properly. The Flash lock resets after each write or erase; the key codes must be written again before a following Flash operation can be per- formed ...
Page 137
... Data is written and erased using the MOVX write instruction (as described in Section 13.1.2 and Section 13.1.3) and read using the MOVC instruction. Note: MOVX read instructions always target XRAM. C8051F360/1/2/3/4/5/6/7/8/9 Rev. 1.0 137 ...
Page 138
... Flash Security Lock Byte is unlocked when no other Flash pages are locked (all bits of the Lock Byte are ‘1’) and locked when any other Flash pages are locked (any bit of the Lock Byte is ‘0’). See the example below for an C8051F360. Security Lock Byte: 1’ ...
Page 139
... Locking any Flash page also locks the page containing the Lock Byte. - Once written to, the Lock Byte cannot be modified except by performing a C2 Device Erase user code writes to the Lock Byte, the Lock does not take effect until the next device reset. C8051F360/1/2/3/4/5/6/7/8/9 C2 Debug User Firmware executing from: ...
Page 140
... C8051F360/1/2/3/4/5/6/7/8/9 13.3. Flash Write and Erase Guidelines Any system which contains routines which write or erase Flash memory from software involves some risk that the write or erase routines will execute unintentionally if the CPU is operating outside its specified operating range system clock frequency, or temperature. This accidental execution of Flash modi- ...
Page 141
... CMOS clock. 13. If operating from the external oscillator, switch to the internal oscillator during Flash write or erase operations. The external oscillator can continue to run, and the CPU can switch back to the external oscillator after the Flash operation has completed. C8051F360/1/2/3/4/5/6/7/8/9 Rev. 1.0 141 ...
Page 142
... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 13.1. SFR Page: 0 SFR Address: 0x8F R/W R/W R/W – – – Bit7 Bit6 Bit5 Bits 7–2: UNUSED. Read = 000000b, Write = don't care. Bit 1: PSEE: Program Store Erase Enable. Setting this bit allows an entire page of the Flash program memory to be erased provided the PSWE bit is also set ...
Page 143
... Important Note: When changing the FLRT bits to a lower setting (e.g. when changing from a value of 11b to 00b), cache reads, cache writes, and the prefetch engine should be disabled using the CCH0CN register (see SFR Definition 14.1). C8051F360/1/2/3/4/5/6/7/8/9 FLSCL: Flash Memory Control R/W ...
Page 144
... C8051F360/1/2/3/4/5/6/7/8/9 Table 13.2. Flash Electrical Characteristics V = 2.7 to 3.6 V; –40 to +85 °C. DD Parameter Conditions C8051F360/1/2/3/4/5/6/7 Flash Size C8051F368/9 Endurance Erase Cycle Time Write Cycle Time *Note: 1024 Bytes at location 0x7C00 to 0x7FFF are reserved. 144 Min Typ Max 32768* 16384 20 k 250 Rev. 1.0 ...
Page 145
... Because the access time of the Flash memory is 40 ns, and the minimum instruction time (C8051F360/1/2/3/4/5/6/ (C8051F368/9), the branch target cache and prefetch engine are nec- essary for full-speed code execution. Instructions are read from Flash memory four bytes at a time by the prefetch engine, and given to the CIP-51 processor core to execute ...
Page 146
... C8051F360/1/2/3/4/5/6/7/8/9 The replacement algorithm is selected with the Cache Algorithm bit, CHALGM (CCH0TN.3). When CHALGM is cleared to ‘0’, the cache will use the rebound algorithm to replace cache locations. The rebound algorithm replaces locations in order from the beginning of cache memory to the end, and then from the end of cache memory to the beginning. When CHALGM is set to ‘ ...
Page 147
... Note that a cache pop should not be initiated if CHSLOT is equal to 11110b. Doing so may have an adverse effect on cache performance. Important: Although locking cache loca- tion 1 is not explicitly disabled by hardware, the entire cache will be unlocked when CHSLOT is equal to 00000b. Therefore, cache locations 1 and 0 must remain unlocked at all times. C8051F360/1/2/3/4/5/6/7/8/9 Rev. 1.0 147 ...
Page 148
... C8051F360/1/2/3/4/5/6/7/8/9 Cache Push Operations Decrement CHSLOT CHSLOT = 27 Cache Pop Operations Increment CHSLOT Figure 14.3. Cache Lock Operation 148 TAG 0 SLOT 0 TAG 1 SLOT 1 TAG 2 SLOT 2 TAG 26 SLOT 26 TAG 27 SLOT 27 TAG 28 SLOT 28 TAG 29 SLOT 29 TAG 30 SLOT 30 TAG 31 SLOT 31 Rev. 1.0 Lock Status UNLOCKED ...
Page 149
... Data requested by MOVC instructions will be loaded into cache memory. Bit 0: CHBLKW: Block Write Enable. This bit allows block writes to Flash memory from software. 0: Each byte of a software Flash write is written individually. 1: Flash bytes are written in groups of four (for code space writes). C8051F360/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W CHRETI ...
Page 150
... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 14.2. CCH0TN: Cache Tuning SFR Page: F SFR Address: 0xC9 R/W R/W R/W CHMSCTL Bit7 Bit6 Bit5 Bits 7–4: CHMSCTL: Cache Miss Penalty Accumulator (Bits 4–1). These are bits 4-1 of the Cache Miss Penalty Accumulator. To read these bits, they must first be latched by reading the CHMSCTH bits in the CCH0MA Register (See SFR Definition 14 ...
Page 151
... Cache performance. Bit 5: RESERVED. Read = 0b. Must Write 0b. Bits 4–0: CHSLOT: Cache Slot Pointer. These read-only bits are the pointer into the cache lock stack. Locations above CHSLOT are locked, and will not be changed by the processor, except when CHSLOT equals 0. C8051F360/1/2/3/4/5/6/7/8 CHSLOT ...
Page 152
... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 14.4. CCH0MA: Cache Miss Accumulator SFR Page: F SFR Address: 0xD3 R R/W R/W CHMSOV Bit7 Bit6 Bit5 Bit 7: CHMSOV: Cache Miss Penalty Overflow. This bit indicates when the Cache Miss Penalty Accumulator has overflowed since it was last written. 0: The Cache Miss Penalty Accumulator has not overflowed since it was last written. ...
Page 153
... External Data Memory Interface and On-Chip XRAM For C8051F36x devices, 1k Bytes of RAM are included on-chip and mapped into the external data memory space (XRAM). Additionally, an External Memory Interface (EMIF) is available on the C8051F360/3 devices, which can be used to access off-chip data memories and memory-mapped devices connected to the GPIO ports ...
Page 154
... C8051F360/1/2/3/4/5/6/7/8/9 15.2. Configuring the External Memory Interface Configuring the External Memory Interface consists of five steps: 1. Configure the Output Modes of the associated port pins as either push-pull or open-drain (push-pull is most common), and skip the associated pins in the crossbar. 2. Configure Port latches to “park” the EMIF pins in a dormant state (usually by setting them to logic ‘ ...
Page 155
... Table 15.1. EMIF Pinout (C8051F360/3) Multiplexed Mode Signal Name Port Pin /RD /WR ALE D0/A0 D1/A1 D2/A2 D3/A3 D4/A4 D5/A5 D6/A6 D7/ A10 A11 A12 A13 A14 A15 – – – – – – – – SFR Definition 15.1. EMI0CN: External Memory Interface Control ...
Page 156
... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 15.2. EMI0CF: External Memory Configuration SFR Page: F SFR Address: 0xC7 R/W R/W R/W – – – Bit7 Bit6 Bit5 Bits 7–5: UNUSED. Read = 000b. Write = don’t care. Bit 4: EMD2: EMIF Multiplex Mode Select. 0: EMIF operates in multiplexed address/data mode. ...
Page 157
... Bus controls the state of the AD[7:0] port at the time /RD or /WR is asserted. See Section “15.6.2. Multiplexed Mode” on page 165 for more information. A[15:8] ALE E AD[7:0] ADDRESS/DATA BUS /WR /RD Figure 15.1. Multiplexed Configuration Example C8051F360/1/2/3/4/5/6/7/8/9 ADDRESS BUS 74HC373 (Optional) 8 Rev. 1.0 A[15:8] A[7:0] ...
Page 158
... C8051F360/1/2/3/4/5/6/7/8/9 15.4.2. Non-multiplexed Configuration In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a Non-multiplexed Configuration is shown in Figure 15.2. See Section “15.6.1. Non-multiplexed Mode” on page 162 for more information about Non-multiplexed operation. A[15: D[7:0] F /WR /RD Figure 15 ...
Page 159
... A[7:0] are driven, determined R1. • 16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip or off-chip, and unlike 8-bit MOVX operations, the full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction. C8051F360/1/2/3/4/5/6/7/8/9 EMI0CF[3: EMI0CF[3: 0xFFFF 0xFFFF ...
Page 160
... C8051F360/1/2/3/4/5/6/7/8/9 15.5.3. Split Mode with Bank Select When EMI0CF.[3:2] are set to ‘10’, the XRAM memory map is split into two areas, on-chip space and off-chip space. • Effective addresses below the internal XRAM size boundary will access on-chip XRAM space. ...
Page 161
... SYSCLK cycles. Bits 1–0: EAH1–0: EMIF Address Hold Time Bits. 00: Address hold time = 0 SYSCLK cycles. 01: Address hold time = 1 SYSCLK cycle. 10: Address hold time = 2 SYSCLK cycles. 11: Address hold time = 3 SYSCLK cycles. C8051F360/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W EWR2 ...
Page 162
... C8051F360/1/2/3/4/5/6/7/8/9 15.6.1. Non-multiplexed Mode 15.6.1.1.16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’. ADDR[15:8] P3.4–P4.3 ADDR[7:0] P2 DATA[7:0] P1 /WR P4.5 /RD P4.4 ADDR[15:8] P3.4–P4.3 ADDR[7:0] P2 DATA[7:0] P1 /RD P4.4 /WR P4.5 Figure 15.4. Non-multiplexed 16-bit MOVX Timing 162 Nonmuxed 16-bit WRITE EMIF ADDRESS (8 MSBs) from DPH ...
Page 163
... P4.4 ADDR[15:8] ADDR[7:0] P2 DATA[7:0] P1 /RD P4.4 /WR P4.5 Figure 15.5. Non-multiplexed 8-bit MOVX without Bank Select Timing C8051F360/1/2/3/4/5/6/7/8/9 Nonmuxed 8-bit WRITE without Bank Select P3.4-P4.3 EMIF ADDRESS (8 LSBs) from EMIF WRITE DATA T WDS T T ACS ACW Nonmuxed 8-bit READ without Bank Select P3 ...
Page 164
... C8051F360/1/2/3/4/5/6/7/8/9 15.6.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’. ADDR[15:8] P3.4–P4.3 ADDR[7:0] P2 DATA[7:0] P1 /WR P4.5 P4.4 /RD ADDR[15:8] P3.4–P4.3 ADDR[7:0] P2 DATA[7:0] P1 /RD P4.4 /WR P4.5 Figure 15.6. Non-multiplexed 8-bit MOVX with Bank Select Timing 164 Nonmuxed 8-bit WRITE with Bank Select ...
Page 165
... ADDR[15:8] P3.4–P4.3 EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE P0.0 /RD P4.4 /WR P4.5 Figure 15.7. Multiplexed 16-bit MOVX Timing C8051F360/1/2/3/4/5/6/7/8/9 Muxed 16-bit WRITE EMIF ADDRESS (8 MSBs) from DPH EMIF WRITE DATA DPL T ALEL T WDS T T ACS ACW Muxed 16-bit READ EMIF ADDRESS (8 MSBs) from DPH ...
Page 166
... C8051F360/1/2/3/4/5/6/7/8/9 15.6.2.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’. ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE P0.0 /WR P4.5 /RD P4.4 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE P0.0 /RD P4.4 /WR P4.5 Figure 15.8. Multiplexed 8-bit MOVX without Bank Select Timing ...
Page 167
... AD[7: ALEH ALE P0.0 /RD P4.4 /WR P4.5 Figure 15.9. Multiplexed 8-bit MOVX with Bank Select Timing C8051F360/1/2/3/4/5/6/7/8/9 Muxed 8-bit WRITE with Bank Select EMIF ADDRESS (8 MSBs) from EMI0CN EMIF WRITE DATA T ALEL T WDS T T ACS ACW Muxed 8-bit READ with Bank Select ...
Page 168
... C8051F360/1/2/3/4/5/6/7/8/9 Table 15.2. AC Parameters for External Memory Interface Parameter Description T Address/Control Setup Time ACS T Address/Control Pulse Width ACW T Address/Control Hold Time ACH T Address Latch Enable High Time ALEH T Address Latch Enable Low Time ALEL T Write Data Setup Time WDS T Write Data Hold Time ...
Page 169
... Electrical specifications for the precision internal oscillator are given in Table 16.1 on page 171 and Table 16.2 on page 172. Note that the system clock may be derived from the programmed internal oscilla- tor divided defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following a reset. C8051F360/1/2/3/4/5/6/7/8/9 OSCICL OSCICN AV+ ...
Page 170
... C8051F360/1/2/3/4/5/6/7/8/9 16.1.1. Internal Oscillator Suspend Mode When software writes a logic ‘1’ to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the sys- tem clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped until one of the following events occur: • ...
Page 171
... The low-frequency oscillator circuit includes a divider that can be changed to divide the clock using the OSCLD bits in the OSCLCN register (see SFR Definition 16.3). Additionally, the OSCLF bits (OSCLCN5:2) can be used to adjust the oscillator’s output frequency. C8051F360/1/2/3/4/5/6/7/8/9 R R/W ...
Page 172
... C8051F360/1/2/3/4/5/6/7/8/9 16.2.1. Calibrating the Internal L-F Oscillator Timers 2 and 3 include capture functions that can be used to capture the oscillator frequency, when run- ning from a known time base. When either Timer 2 or Timer 3 is configured for L-F Oscillator Capture Mode, a falling edge (Timer 2) or rising edge (Timer 3) of the low-frequency oscillator’s output will cause a capture event on the corresponding timer ...
Page 173
... Important Note on External Oscillator Usage: Port pins must be configured when using the external oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins P0.5 and P0.6 (C8051F360/3) or P0.2 and P0.3 (C8051F361/2/4/5/6/7/8/9) are used as XTAL1 and XTAL2 respectively. When the external oscillator drive circuit is enabled in capacitor, RC, or CMOS clock mode, Port pin P0.6 (C8051F360/3) or P0.3 (C8051F361/2/4/5/6/7/8/9) is used as XTAL2. The Port I/O Crossbar should be configured to skip the Port pins used by the oscillator circuit ...
Page 174
... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 16.4. CLKSEL: System Clock Selection SFR Page: F SFR Address: 0x8F R/W R/W R/W Reserved Reserved CLKDIV1 CLKDIV0 Reserved CLKSL2 Bit7 Bit6 Bit5 Bits 7–6: RESERVED. Read = 00b. Must Write 00b. Bits 5–4: CLKDIV1-0: Output SYSCLK Divide Factor. These bits can be used to pre-divide SYSCLK before it is output to a port pin through the crossbar ...
Page 175
... R = Pullup resistor value in kΩ C MODE (Circuit from Figure 16.1, Option 3; XOSCMD = 10x) Choose K Factor (KF) for the oscillation frequency desired KF/( where frequency of oscillation in MHz C = capacitor value on XTAL1, XTAL2 pins Power Supply on MCU in Volts DD C8051F360/1/2/3/4/5/6/7/8/9 R/W R R/W R/W XFCN2 XFCN1 Bit4 Bit3 Bit2 Bit1 RC (XOSCMD = 100) f ≤ ...
Page 176
... C8051F360/1/2/3/4/5/6/7/8/9 16.5. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 16.1, Option 1. The External Oscillator Frequency Control value (XFCN) should be chosen from the Crystal column of the table in SFR Definition 16.5 (OSCXCN register). For example ...
Page 177
... MHz = 3.0) Since the frequency of roughly 75 kHz is desired, select the K Factor from the table in SFR Definition 16 7.7: 0.075 MHz = 7 3. 3.0 = 7.7 / 0.075 MHz C = 102 34.2 pF Therefore, the XFCN value to use in this example is 010b. C8051F360/1/2/3/4/5/6/7/8/9 Rev. 1.0 = 3.0 V and DD 177 ...
Page 178
... C8051F360/1/2/3/4/5/6/7/8/9 16.8. Phase-Locked Loop (PLL) A Phase-Locked-Loop (PLL) is included, which is used to multiply the internal oscillator or an external clock source to achieve higher CPU operating frequencies. The PLL circuitry is designed to produce an output frequency between 25 MHz and 100 MHz, from a divided reference frequency between 5 MHz and 30 MHz ...
Page 179
... Section “13. Flash Memory” on page 135). Important Note: Cache reads, cache writes, and the prefetch engine should be disabled whenever the FLRT bits are changed to a lower setting. C8051F360/1/2/3/4/5/6/7/8/9 Rev. 1.0 179 ...
Page 180
... C8051F360/1/2/3/4/5/6/7/8/9 To shut down the PLL, the system clock should be switched to the internal oscillator or a stable external clock source, using the CLKSEL register. Next, disable the PLL by setting PLLEN (PLL0CN.1) to ‘0’. Finally, the PLL can be powered off, by setting PLLPWR (PLL0CN.0) to ‘0’. Note that the PLLEN and PLL- PWR bits can be cleared at the same time ...
Page 181
... Bits 3–0: PLLLP3-0: PLL Loop Filter Control Bits. Selection is based on the divided PLL reference clock, according to the following table: Divided PLL Reference Clock 19–30 MHz 12.2–19.5 MHz 7.8–12.5 MHz 5–8 MHz All other states of PLLLP3–0 are RESERVED. C8051F360/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W PLLN4 PLLN3 PLLN2 ...
Page 182
... C8051F360/1/2/3/4/5/6/7/8/9 Table 16.3. PLL Frequency Characteristics –40 to +85 °C unless otherwise specified. Parameter Input Frequency (Divided Reference Frequency) PLL Output Frequency *Note: The maximum operating frequency of the C8051F366/7/8 MHz. Table 16.4. PLL Lock Timing Characteristics –40 to +85 °C unless otherwise specified ...
Page 183
... Port Input/Output Digital and analog resources are available through I/O pins. On the largest devices (C8051F360/3), port pins are organized as four byte-wide Ports and one 7-bit-wide Port. On the other devices (C8051F361/2/4/5/6/7/8/9), port pins are three byte-wide Ports and one partial port. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input/output ...
Page 184
... C8051F360/1/2/3/4/5/6/7/8/9 /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT Analog Select ANALOG INPUT PORT-INPUT Figure 17.2. Port I/O Cell Block Diagram 184 VIO VIO (WEAK) GND Rev. 1.0 PORT PAD ...
Page 185
... UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding UART0, which will be assigned to specific port pins (P0.1 and P0.2 in the C8051F360/3 devices, P0.4 and P0.5 in the C8051F361/2/4/5/6/7/8/9 devices Port pin is assigned, the Crossbar skips that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose associated bits in the PnSKIP registers are set ...
Page 186
... SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.1 (C8051F360/3) or P0.4 (C8051F361/2/4/5/6/7/8/9); UART RX0 is always assigned to P0.2 (C8051F360/3) or P0.5 (C8051F361/2/4/5/6/7/8/9). Standard Port I/Os appear contiguously starting at P0.0 after prioritized functions and skipped pins are assigned ...
Page 187
... Table alternative, the Configuration Wizard utility of the Silicon Labs IDE software will determine the Port I/O pin-assignments based on the XBRn Register settings. The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers are disabled while the Crossbar is disabled. C8051F360/1/2/3/4/5/6/7/8/9 Rev. 1.0 187 ...
Page 188
... SPI I/O routed to Port pins. Note that the SPI can be assigned either GPIO pins. Bit 0: URT0E: UART I/O Output Enable 0: UART I/O unavailable at Port pin. 1: UART TX0, RX0 routed to Port pins P0.1 and P0.2 (C8051F360/3) or P0.4 and P0.5 (C8051F361/2/4/5/6/7/8/9). 188 R/W ...
Page 189
... CEX0, CEX1, CEX2 routed to Port pins. 100: CEX0, CEX1, CEX2, CEX3 routed to Port pins. 101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins. 110: CEX0, CEX1, CEX2, CEX3, CEX4, CEX5 routed to Port pins. 111: Reserved. C8051F360/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W ...
Page 190
... Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for general purpose I/O. Ports P0-P3 are accessed through corresponding special function registers (SFRs) that are both byte-addressable and bit-addressable. Port 4 (C8051F360/3 only) uses an SFR which is byte-addressable. When writing to a Port, the value written to the SFR is latched to maintain the output data value at each pin ...
Page 191
... Bits 7–0: Output Configuration Bits for P0.7-P0.0 (respectively): ignored if corresponding bit in regis- ter P0MDIN is logic ‘0’. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n Output is push-pull. Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless of the value of P0MDOUT. C8051F360/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W Bit4 Bit3 ...
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... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.6. P0SKIP: Port0 Skip SFR Page: F SFR Address: 0xD4 R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: P0SKIP[7:0]: Port0 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana- log inputs (for ADC or Comparator) or used as special functions (V lator circuit, CNVSTR input) should be skipped by the Crossbar ...
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... Bits 7–0: Analog Input Configuration Bits for P1.7-P1.0 (respectively). Port pins configured as analog inputs have their weak pullup, digital driver, and digital receiver disabled. 0: Corresponding P1.n pin is configured as an analog input. 1: Corresponding P1.n pin is not configured as an analog input. C8051F360/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W P1 ...
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... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.11. P1MDOUT: Port1 Output Mode SFR Page: F SFR Address: 0xA5 R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: Output Configuration Bits for P1.7-P1.0 (respectively): ignored if corresponding bit in regis- ter P1MDIN is logic ‘0’. 0: Corresponding P1.n Output is open-drain. 1: Corresponding P1.n Output is push-pull. ...
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... Logic Low Output. 1: Logic High Output (high impedance if corresponding P2MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P2MDIN. Directly reads Port pin when configured as digital input. 0: P2.n pin is logic low. 1: P2.n pin is logic high. C8051F360/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W Bit4 ...
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... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.16. P2MDIN: Port2 Input Mode SFR Page: F SFR Address: 0xF3 R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: Analog Input Configuration Bits for P2.7-P2.0 (respectively). Port pins configured as analog inputs have their weak pullup, digital driver, and digital receiver disabled ...
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... Bits 7–0: P2MASK[7:0]: Port2 Mask Value. These bits select which Port pins will be compared to the value stored in P2MAT. 0: Corresponding P2.n pin is ignored and cannot cause a Port Match event. 1: Corresponding P2.n pin is compared to the corresponding bit in P2MAT. C8051F360/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W ...
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... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.21. SFR Page: all pages (bit addressable) SFR Address: 0xB0 R/W R/W R/W P3.7 P3.6 P3.5 Bit7 Bit6 Bit5 Bits 7–0: P3.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P3MDOUT.n bit = 0). ...
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... These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana- log inputs (for ADC or Comparator) or used as special functions (V lator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P3.n pin is not skipped by the Crossbar. 1: Corresponding P3.n pin is skipped by the Crossbar. C8051F360/1/2/3/4/5/6/7/8/9 P3MDOUT: Port3 Output Mode R/W R/W R/W ...
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... C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.25. SFR Page: all pages SFR Address: 0xB5 R R/W R/W – P4.6 P4.5 Bit7 Bit6 Bit5 Bit 7: UNUSED. Read = 0b. Write = don’t care. Bits 6–0: P4.[6:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P4MDOUT.n bit = 0). ...