C8051F015-GQ Silicon Laboratories Inc, C8051F015-GQ Datasheet - Page 128

• Manufacturer Part Number: C8051F015-GQ
• Description: IC 8051 MCU 32K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F01xr

Specifications of C8051F015-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 64-TQFP, 64-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F005DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 2-ch x 12-bit
• Package: 64TQFP
• Device Core: 8051
• Family Name: C8051F01x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1194

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
SPIF
R/W
Bit7
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled,
setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is
not automatically cleared by hardware. It must be cleared by software.
WCOL: Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI interrupt) to indicate a write to
the SPI data register was attempted while a data transfer was in progress. It is cleared by
software.
This bit is set to logic 1 by hardware (and generates a SPI interrupt) when a master mode
collision is detected (NSS is low and MSTEN = 1). This bit is not automatically cleared by
hardware. It must be cleared by software.
This bit is set to logic 1 by hardware (and generates a SPI interrupt) when the receive
buffer still holds unread data from a previous transfer and the last bit of the current transfer
is shifted into the SPI shift register. This bit is not automatically cleared by hardware. It
must be cleared by software.
This bit is set to logic 1 by hardware while a master mode transfer is in progress. It is
cleared by hardware at the end of the transfer.
This bit is set to logic 1 whenever the NSS pin is low indicating it is enabled as a slave. It
is cleared to logic 0 when NSS is high (slave disabled).
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
This bit enables/disables the SPI.
0: SPI disabled.
1: SPI enabled.
SPIF: SPI Interrupt Flag.
MODF: Mode Fault Flag.
RXOVRN: Receive Overrun Flag.
TXBSY: Transmit Busy Flag.
SLVSEL: Slave Selected Flag.
MSTEN: Master Mode Enable.
SPIEN: SPI Enable.
WCOL
R/W
Bit6
Figure 17.6. SPI0CN: SPI Control Register
MODF
R/W
Bit5
RXOVRN
R/W
Bit4
Rev. 1.7
TXBSY
Bit3
R
SLVSEL
Bit2
R
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
MSTEN
R/W
Bit1
(bit addressable)
SPIEN
R/W
Bit0
SFR Address:
Reset Value
00000000
0xF8
128