ADUC7129BSTZ126-RL Analog Devices Inc, ADUC7129BSTZ126-RL Datasheet - Page 47

• Manufacturer Part Number: ADUC7129BSTZ126-RL
• Description: IC DAS MCU ARM7 ADC/DDS 80-LQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7129BSTZ126-RL

• Core Size: 16/32-Bit
• Program Memory Size: 126KB (126K x 8)
• Core Processor: ARM7
• Speed: 41.78MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: PLA, POR, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 38
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-LQFP
• Controller Family/series: (ARM7) ADUC
• No. Of I/o's: 40
• Cpu Speed: 41.78MHz
• No. Of Timers: 5
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: ADUC7129BSTZ126-RLTR

DDSFRQ Register
Name
DDSFRQ
Table 54. DDSFRQ MMR Bit Designations
Bit
31:0
The DDS frequency is controlled via the DDSFRQ MMR. This
MMR contains a 32-bit word (FSW) that controls the frequency
according to the following formula:
DDSPHS Register
Name
DDSPHS
Table 55. DDSPHS MMR Bit Designations
Bit
31:12
11:0
The DDS phase offset is controlled via the DDSPHS MMR. This
MMR contains a 12-bit value that controls the phase of the DDS
output according to the following formula:
POWER SUPPLY MONITOR
The power supply monitor on the ADuC7128/ADuC7129
indicates when the IOV
supply trip points. The monitor function is controlled via the
PSMCON register (see Table 56). If enabled in the IRQEN or
FIQEN register, the monitor interrupts the core using the PSMI
bit in the PSMCON MMR. This bit is cleared immediately once
CMP goes high. Note that if the interrupt generated is exited
before CMP goes high (IOV
interrupts are generated until CMP returns high. The user should
ensure that code execution remains within the ISR until CMP
returns high.
Table 56. PSMCON MMR Bit Designations
Bit
3
2
1
0
Frequency
Phase
Name
CMP
TP
PSMEN
PSMI
Offset
Address
0xFFFF0694
Description
Frequency select word (FSW)
Address
0xFFFF0698
Description
Reserved
Phase
=
=
FSW
2
×
π
×
DD
2
×
20
12
supply pin drops below one of two
Phase
DD
2
.
8896
32
is above the trip point), no further
Description
Comparator Bit. This is a read-only bit that directly reflects the state of the comparator.
Trip Point Selection Bit.
Power Supply Monitor Enable Bit.
Power Supply Monitor Interrupt Bit. This bit is set high by the MicroConverter if CMP is low, indicating low
I/O supply. The PSMI bit can be used to interrupt the processor. Once CMP returns high, the PSMI bit can
be cleared by writing a 1 to this location. A write of 0 has no effect. There is no timeout delay. PSMI can be
cleared immediately once CMP goes high.
Default Value
0x00000000
Default Value
0x00000000
MHz
Read 1 indicates the IOV
Read 0 indicates the IOV
the interrupt service routine.
0 = 2.79 V
1 = 3.07 V
Set to 1 by the user to enable the power supply monitor circuit.
Cleared to 0 by the user to disable the power supply monitor circuit.
Access
R/W
Access
R/W
DD
DD
Rev. 0 | Page 47 of 92
supply is above its selected trip point or the PSM is in power-down mode.
supply is below its selected trip point. This bit should be set before leaving
This monitor function allows the user to save working registers
to avoid possible data loss due to the low supply or brown-out
conditions. It also ensures that normal code execution does not
resume until a safe supply level has been established.
The PSM does not operate correctly when using JTAG debug.
It should be disabled in JTAG debug mode.
COMPARATOR
The ADuC7128/ADuC7129 integrate an uncommitted voltage
comparator. The positive input is multiplexed with ADC2, and
the negative input has two options: ADC3 or the internal refer-
ence. The output of the comparator can be configured to generate
a system interrupt, can be routed directly to the programmable
logic array, can start an ADC conversion, or can be on an
external pin, CMP
Hysteresis
Figure 47 shows how the input offset voltage and hysteresis
terms are defined. Input offset voltage (V
between the center of the hysteresis range and the ground level.
This can either be positive or negative. The hysteresis voltage
(V
H
P0.0/CMP
) is ½ the width of the hysteresis range.
ADC2/CMP0
ADC3/CMP1
OUT
Figure 47. Comparator Hysteresis Transfer Function
COMP
REF
OUT
OUT
.
V
Figure 46. Comparator
OS
MUX
V
H
ADuC7128/ADuC7129
V
H
MUX
OS
COMP0
) is the difference
PLA
IRQ
ADC START
CONVERSION