DS80C390-FNR+ Maxim Integrated Products, DS80C390-FNR+ Datasheet - Page 33

• Manufacturer Part Number: DS80C390-FNR+
• Description: IC MPU CAN DUAL HS IND 64-LQFP
• Manufacturer: Maxim Integrated Products
• Series: 80Cr

Specifications of DS80C390-FNR+

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.85 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: DS80C390
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Size: 4 KB
• Data Ram Size: 4 KB
• Interface Type: CAN, IrDA
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 3.85 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Package: 64LQFP
• Device Core: 8051
• Family Name: 80C
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

ON-CHIP ARITHMETIC ACCELERATOR
An on-chip math accelerator allows the microcontroller to perform 32-bit and 16-bit multiplication, division, shifting,
and normalization using dedicated hardware. Math operations are performed by sequentially loading three special
registers. The mathematical operation is determined by the sequence in which three dedicated SFRs (MA, MB, and
MC) are accessed, eliminating the need for a special step to choose the operation. The normalize function
facilitates the conversion of 4-byte unsigned binary integers into floating point format.
supported by the math accelerator and their time of execution.
Table 2. Arithmetic Accelerator Execution Times
Table 3
MA and MB registers must be loaded and read in the order shown for proper operation, although accesses to any
other registers can be performed between access to the MA or MB registers. An access to the MA, MB, or MC
registers out of sequence corrupts the operation, requiring the software to clear the MST bit to restart the math
accelerator state machine. Consult the description of the MCNT0 SFR for details of how the shift and normalize
functions operate.
Software must ensure that the input value for the normalize operation is not zero or the function will not complete.
Compilers such as the one from Keil Software have updated their libraries and compensate for this condition.
Table 3. Arithmetic Accelerator Sequencing
*
**
***Value to be normalized must be nonzero.
Not performed for 16-bit numerator.
Load MA with dividend LSB.
Load MA with dividend LSB + 1.*
Load MA with dividend LSB + 2.*
Load MA with dividend MSB.
Load MB with divisor LSB.
Load MB with divisor MSB.
Poll the MST bit until cleared. (9 machine cycles).
Read MA to retrieve the quotient MSB.
Read MA to retrieve the quotient LSB + 2.**
Read MA to retrieve the quotient LSB + 1.**
Read MA to retrieve the quotient LSB.
Read MB to retrieve the remainder MSB.
Read MB to retrieve the remainder LSB.
Load MA with data LSB.
Load MA with data LSB + 1.
Load MA with data LSB + 2.
Load MA with data MSB.
Configure MCNT0 register as required
Poll the MST bit until cleared. (9 machine cycles)
Read MA for result MSB.
Read MA for result LSB + 2.
Read MA for result LSB + 1.
Read MA for result LSB.
Not performed for 16/16 divide.
32-Bit Shift Left/Right
16-Bit/16-Bit Multiply
32-Bit/16-Bit Divide
16-Bit/16-Bit Divide
32-Bit Normalize
OPERATION
demonstrates the procedure to perform mathematical operations using the hardware math accelerator. The
DIVIDE (32/16 OR 16/16)
SHIFT RIGHT/LEFT
32-Bit Quotient, 16-Bit Remainder
16-Bit Quotient, 16-Bit Remainder
32-Bit Mantissa, 5-Bit Exponent
32-Bit Product
32-Bit Result
RESULT
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Load MB with multiplier LSB.
Load MB with multiplier MSB.
Load MA with multiplicand LSB.
Load MA with multiplicand MSB.
Poll the MST bit until cleared. (6 machine cycles).
Read MA for product MSB.
Read MA for product LSB + 2.
Read MA for product LSB + 1.
Read MA for product LSB.
Load MA with data LSB.
Load MA with data LSB + 1.
Load MA with data LSB + 2.
Load MA with data MSB.***
Load MCNT0 with 00h.
Poll the MST bit until cleared. (9 machine cycles)
Read MA for mantissa MSB.
Read MA for mantissa LSB + 2.
Read MA for mantissa LSB + 1.
Read MA for mantissa LSB.
Read MCNT0.4–MCNT0.0 for exponent.
EXECUTION TIME
(t
CLCL
36
24
24
36
36
MULTIPLY (16 X 16)
)
NORMALIZE
Table 2
shows the operations