PIC12F509-I/SM Microchip Technology, PIC12F509-I/SM Datasheet - Page 4

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PIC12F509-I/SM

Manufacturer Part Number
PIC12F509-I/SM
Description
IC PIC MCU FLASH 1KX12 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Fr

Specifications of PIC12F509-I/SM

Program Memory Type
FLASH
Program Memory Size
1.5KB (1K x 12)
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Ram Size
41 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC12F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
41 B
Interface Type
RS- 232/USB
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
6
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164101, DM163014, DV164120, DM163029
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162059 - HEADER INTRFC MPLAB ICD2 8/14PINDVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICE
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC12F509-I/SM
Manufacturer:
AOS
Quantity:
9 000
Part Number:
PIC12F509-I/SM
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC12F508/509
3.1.2.1
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as
described previously. Because this is a 12-bit core, the
two MSbs of the data word are ignored. A timing
diagram for the Load Data command is shown in
Figure 3-1.
FIGURE 3-2:
3.1.2.2
After receiving this command, the chip will transmit
data bits out of the program memory (user or
configuration) currently addressed, starting with the
second rising edge of the clock input. The data pin will
go into Output mode on the second rising clock edge,
and it will revert to Input mode (high-impedance) after
the 16th rising edge. Because this is a 12-bit core, the
two MSbs of the 14-bit word will be read as ‘0’s.
If the program memory is code-protected (CP = 0),
portions of the program memory will be read as zeros.
See Section 5.0 “Code Protection” for details.
FIGURE 3-3:
DS41227E-page 4
ICSPCLK
ICSPDAT
ICSPCLK
ICSPDAT
Load Data For Program Memory
Read Data From Program Memory
1
1
LOAD DATA COMMAND (PROGRAM/VERIFY)
READ DATA FROM PROGRAM MEMORY COMMAND
0
0
1
T
SET
2
0
1
2
1
1
T
3
SET
T
0
3
HLD
input
1
T
1
HLD
4
0
0
4
1
5
5
x
x
Preliminary
T
6
DLY
x
6
x
T
T
1
T
DLY
DLY
DLY
2
2
1
1
strt_bit
1
strt_bit
2
2
LSb
LSb
T
3
T
SET
DLY
3
-+
T
1
3
HLD
4
1
4
output
© 2007 Microchip Technology Inc.
5
5
15
MSb
15
16
MSb
stp_bit
16
stp_bit
input

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