PIC16F1827-I/P Microchip Technology, PIC16F1827-I/P Datasheet - Page 82

• Manufacturer Part Number: PIC16F1827-I/P
• Description: IC PIC MCU FLASH 4K 18-DIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1827-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F/LF1826/27
7.10
Upon any Reset, multiple bits in the STATUS and
PCON register are updated to indicate the cause of the
Reset. Table 7-3 and Table 7-4 show the Reset condi-
tions of these registers.
TABLE 7-3:
TABLE 7-4:
DS41391C-page 82
Power-on Reset
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Reset
WDT Wake-up from Sleep
Brown-out Reset
Interrupt Wake-up from Sleep
RESET Instruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
STKOVF STKUNF RMCLR
0
0
0
0
u
u
u
u
u
u
1
u
2: If a Status bit is not implemented, that bit will be read as ‘0’.
Determining the Cause of a Reset
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
0
0
0
0
u
u
u
u
u
u
u
1
RESET STATUS BITS AND THEIR SIGNIFICANCE
RESET CONDITION FOR SPECIAL REGISTERS
Condition
1
1
1
1
u
u
u
0
0
u
u
u
RI
1
1
1
1
u
u
u
u
u
0
u
u
POR
0
0
0
u
u
u
u
u
u
u
u
u
Preliminary
BOR
x
x
x
0
u
u
u
u
u
u
u
u
TO
1
0
x
1
0
0
1
u
1
u
u
u
Program
PC + 1
Counter
PC + 1
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
PD
1
x
0
1
u
0
0
u
0
u
u
u
(1)
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up from Sleep
Interrupt Wake-up from Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
RESET Instruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
(2)
---1 1000
---u uuuu
---1 0uuu
---0 uuuu
---0 0uuu
---1 1uuu
---1 0uuu
---u uuuu
---u uuuu
---u uuuu
Register
STATUS
 2010 Microchip Technology Inc.
Condition
00-- 110x
uu-- 0uuu
uu-- 0uuu
uu-- uuuu
uu-- uuuu
00-- 11u0
uu-- uuuu
uu-- u0uu
1u-- uuuu
u1-- uuuu
Register
PCON