C8051F586-IM Silicon Laboratories Inc, C8051F586-IM Datasheet
C8051F586-IM
Manufacturer Part Number
C8051F586-IM
Description
IC 8051 MCU 96K FLASH 32-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F58xr
Datasheet
1.C8051F586-IQ.pdf
(1 pages)
Specifications of C8051F586-IM
Program Memory Type
FLASH
Program Memory Size
96KB (96K x 8)
Package / Case
32-QFN
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 25x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8448 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
25
Number Of Timers
6
Operating Supply Voltage
1.8 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F580DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 32 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1577-5
Analog Peripherals
12-Bit ADC, 5 V input signal; up to 25 external inputs
-
-
-
-
Built-in Temperature Sensor (±3 °C)
Three Comparators
Precision Internal Voltage Reference
V
On-Chip Debug
-
-
-
-
Temperature Range: –40 to +125 °C
Operating Voltage: 1.8 to 5.25 V
-
Development Kit: C8051F580DK
Automotive
DD
±1 LSB INL; guaranteed monotonic
Programmable throughput up to 200 ksps
Data-dependent windowed interrupt generator
Programmable gain maximizes input signal span
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watch-points
Inspect/modify memory, registers, and stack
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Multiple power saving sleep and shutdown modes
Monitor/Brown-out Detector
C2CK/RST
VREGIN
GNDA
VDDA
GND
VDD
Internal Oscillator
Programming
C2D
Power On
Hardware
Voltage Regulator
Debug /
Reset
(±0.5%)
System Clock Setup
(LDO)
Reset
Clock Multiplier
CIP-51 8051 Controller
96 kB Flash Program
External Oscillator
50 MIPS, 96 kB Flash, 12-Bit ADC, 32-Pin Automotive MCU
Copyright © 2008 by Silicon Laboratories
XTAL1
Core (50 MHz)
256 Byte RAM
8 kB XRAM
Memory
XTAL2
SFR
Bus
High-Speed 8051 µC Core
-
-
Memory
-
-
CAN 2.0B
-
LIN 2.1
-
Digital Peripherals
-
-
-
-
Clock Sources
-
-
Ordering Part Numbers
-
-
VDD
PCA/WDT
CAN 2.0B
Pipelined instruction architecture; executes 70% of instructions in one or
two system clocks
Up to 50 MIPS throughput
96 kB Flash; in-system programmable; flexible security features
8448 bytes data RAM (256 + 8 kB)
32 message objects
Master or slave operation using dedicated hardware
Up to 25 digital I/O; all are 5 V push-pull
Hardware I
Two independent programmable 16-bit counter array with six capture/
compare modules
Six general-purpose 16-bit counter/timers
Internal programmable ±0.5% oscillator: Up to 50 MHz
External oscillator: Crystal, RC, C, or CMOS Clock
C8051F586-IM, 32-Pin QFN (RoHS-compliant), 5 x 5 mm
C8051F586-IQ, 32-Pin QFP (RoHS-compliant), 9 x 9 mm
Timers 0,
1,2,3,4,5
CP0, CP0A
CP2, CP2A
Comparator 0
Comparator 2
UART0
UART1
channel
LIN 2.1
12-bit
200ksps
ADC
Analog Peripherals
Digital Peripherals
2 x 6
SPI
I2C
Port I/O Configuration
Crossbar Control
Reference
Voltage
VREF
2
+
+
C, SPI™, and two UART serial ports available concurrently
-
-
M
A
U
X
CP1, CP1A
Comparator 1
VREF
Crossbar
Decoder
Priority
VDD
VREF
P0 – P3
Temp
Sensor
GND
+
-
Drivers
Drivers
Drivers
Port 0
Port 1
Port 2
Port 3
Driver
C8051F586
VIO
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
2
2
11.21.2008
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