PIC16F636-E/P Microchip Technology, PIC16F636-E/P Datasheet - Page 3

• Manufacturer Part Number: PIC16F636-E/P
• Description: IC MCU FLASH 2KX14 14DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F636-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LVD, POR, WDT
• Number Of I /o: 11
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 14-DIP (0.300", 7.62mm)
• For Use With: AC164039 - MODULE SKT PROMATE II 20DIP/SOICAC162057 - MPLAB ICD 2 HEADER 14DIPACICE0207 - MPLABICE 14P 300 MIL ADAPTER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Silicon Errata Issues
1. Module: Resets (when WDT times out)
2. Module: Wake-up Reset (WUR)
 2010 Microchip Technology Inc.
Note:
If the OPTION_REG bits, PS<2:0>, are changed
from any other value to ‘000’, multiple spurious
Resets can occur when the WDT times out. These
Resets can occur even when the PSA bit is clear,
assigning the prescaler to the Timer0.
Work around
If a CLRWDT instruction is issued before the WDT
times out and before the OPTION register
PS<2:0> bits are modified, this problem is
eliminated.
This issue was corrected in revision B silicon.
Affected Silicon Revisions
If a Wake-up Reset occurs when the Wake-up
Reset (WURE) and Power-up Timer (PWTRE)
Configuration bits are enabled in revision A silicon,
there will not be a 72 ms time delay as expected.
Work around
There is no work around in revision A silicon for
this errata. However, this issue was corrected for
revision B silicon. If a Wake-up Reset occurs when
the Wake-up Reset and Power-up Timer Configu-
ration bits are enabled in revision B silicon, there
will be a nominal 72 ms time delay following the
Wake-up Reset.
Affected Silicon Revisions
A1
A1
X
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B4).
B3
B3
B4
B4
3. Module: Internal/External Clock Switch
If a Wake-up Reset occurs when the Wake-up
Reset (WURE) and Internal/External Clock Switch
Over (IESO) Configuration bits are enabled in
revision A silicon and there is no external clock
applied to the chip when in the XT/HS
configurations, the processor will hang on a Wake-
up Reset.
Work around
There is no work around in revision A silicon for
this errata. However, this issue was corrected for
revision B silicon. If a Wake-up Reset occurs when
the Wake-up Reset and Internal/External Clock
Switch Over Configuration bits are enabled in
revision B silicon and a Wake-up Reset occurs, the
chip will wake up and reset as expected.
Affected Silicon Revisions
A1
X
B3
Over (IESO)
PIC16F636/639
B4
DS80204H-page 3