PIC12LCE518-04/SN Microchip Technology, PIC12LCE518-04/SN Datasheet - Page 43

• Manufacturer Part Number: PIC12LCE518-04/SN
• Description: IC MCU OTP 512X12 LV W/EE 8SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12LCE518-04/SN

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 768B (512 x 12)
• Program Memory Type: OTP
• Eeprom Size: 16 x 8
• Ram Size: 25 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: PIC12LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 25 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 8
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

8.6.1
The WDT has a nominal time-out period of 18 ms,
(with no prescaler). If a longer time-out period is
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT (under software control)
by writing to the OPTION register. Thus, a time-out
period of a nominal 2.3 seconds can be realized.
These periods vary with temperature, V
part process variations (see DC specs).
Under worst case conditions (V
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
FIGURE 8-12: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 8-6:
N/A
Legend: Shaded boxes = Not used by Watchdog Timer, — = unimplemented, read as ’0’, u = unchanged
Address
1999 Microchip Technology Inc.
WDT PERIOD
OPTION
Name
Note: T0CS, T0SE, PSA, PS2:PS0
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Configuration Bit
WDT Enable
Watchdog
are bits in the OPTION register.
Timer
GPWU
Bit 7
From Timer0 Clock Source
(Figure 8-5)
DD
= Min., Temperature
GPPU
Bit 6
DD
and part-to-
T0CS
1
0
Bit 5
PSA
M
U
X
T0SE
Bit 4
Bit 3
PSA
0
8.6.2
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it
from timing out and generating a device RESET.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum SLEEP time before a WDT wake-up reset.
Time-out
8 - to - 1 MUX
WDT
MUX
Postscaler
Postscaler
Bit 2
PS2
1
WDT PROGRAMMING CONSIDERATIONS
Bit 1
PS1
PSA
To Timer0 (Figure 8-4)
Bit 0
PS0
PS2:PS0
PIC12C5XX
1111 1111
Power-On
Value on
Reset
DS40139E-page 43
1111 1111
All Other
Value on
Resets