PIC16F1823-I/P Microchip Technology, PIC16F1823-I/P Datasheet - Page 309

• Manufacturer Part Number: PIC16F1823-I/P
• Description: IC MCU 8BIT FLASH 14-DIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1823-I/P

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 14-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 KB
• Interface Type: MI2C, SPI, EUSART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

FIGURE 26-12:
TABLE 26-8:
 2010 Microchip Technology Inc.
BAUDCON
INTCON
PIE1
PIR1
RCREG
RCSTA
SPBRGL
SPBRGH
TRISA
TRISC
TXSTA
Legend:
Note 1:
(SCKP = 0)
(SCKP = 1)
(Interrupt)
Note:
TX/CK pin
TX/CK pin
CREN bit
SREN bit
bit SREN
RCIF bit
RCREG
Name
RX/DT
Write to
Read
(2)
2:
pin
*
— = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
Page provides register information.
PIC12F/LF1822 only.
PIC16F/LF1823 only.
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
‘0’
TMR1GIE
TMR1GIF
ABDOVF
CSRC
SPEN
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Bit 7
GIE
—
—
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
bit 0
RCIDL
ADIE
PEIE
ADIF
Bit 6
RX9
TX9
—
—
PIC12F/LF1822/PIC16F/LF1823
bit 1
TRISA5
TMR0IE
TRISC5
SREN
TXEN
RCIE
RCIF
Bit 5
—
EUSART Receive Data Register
(1)
bit 2
TRISA4
Preliminary
TRISC4
CREN
SYNC
SCKP
INTE
Bit 4
TXIE
TXIF
BRG<15:8>
BRG<7:0>
(1)
bit 3
TRISC3
ADDEN
TRISA3
SENDB
BRG16
SSPIE
SSPIF
IOCIE
Bit 3
bit 4
TMR0IF
CCP1IE
CCP1IF
TRISA2
TRISC2
BRGH
FERR
Bit 2
—
bit 5
TMR2IE
TMR2IF
TRISA1
TRISC1
OERR
TRMT
WUE
Bit 1
INTF
bit 6
TMR1IE
TMR1IF
TRISC0
ABDEN
TRISA0
bit 7
IOCIF
RX9D
TX9D
Bit 0
DS41413B-page 309
Register
on Page
290*
297*
297*
296
101
102
105
295
124
128
294
‘0’