AT89C4051-12SU Atmel, AT89C4051-12SU Datasheet - Page 8

IC 8051 MCU FLASH 4K 20SOIC

AT89C4051-12SU

Manufacturer Part Number
AT89C4051-12SU
Description
IC 8051 MCU FLASH 4K 20SOIC
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C4051-12SU

Core Processor
8051
Core Size
8-Bit
Speed
12MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LED, POR
Number Of I /o
15
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
UART
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
15
Number Of Timers
2
Operating Supply Voltage
2.7 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C4051-12SU
Manufacturer:
ATMEL
Quantity:
5 000
Part Number:
AT89C4051-12SU
Manufacturer:
AT
Quantity:
20 000
12. Programming The Flash
8
AT89C4051
The AT89C4051 is shipped with the 4K bytes of on-chip PEROM code memory array in the
erased state (i.e., contents = FFH) and ready to be programmed. The code memory array is pro-
grammed one byte at a time. Once the array is programmed, to re-program any non-blank byte,
the entire memory array needs to be erased electrically.
Internal Address Counter: The AT89C4051 contains an internal PEROM address counter
which is always reset to 000H on the rising edge of RST and is advanced by applying a positive
going pulse to pin XTAL1.
Programming Algorithm: To program the AT89C4051, the following sequence is
recommended.
To Program and Verify the Array:
Data Polling: The AT89C4051 features Data Polling to indicate the end of a write cycle. During
a write cycle, an attempted read of the last byte written will result in the complement of the writ-
ten data on P1.7. Once the write cycle has been completed, true data is valid on all outputs, and
the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.
Ready/Busy: The Progress of byte programming can also be monitored by the RDY/BSY output
signal. Pin P3.1 is pulled low after P3.2 goes High during programming to indicate BUSY. P3.1 is
pulled High again when programming is done to indicate READY.
1. Power-up sequence:
2. Set pin RST to “H”
3. Apply the appropriate combination of “H” or “L” logic
4. Apply data for Code byte at location 000H to P1.0 to P1.7.
5. Raise RST to 12V to enable programming.
6. Pulse P3.2 once to program a byte in the PEROM array or the lock bits. The byte-write
7. To verify the programmed data, lower RST from 12V to logic “H” level and set pins P3.3
8. To program a byte at the next address location, pulse XTAL1 pin once to advance the
9. Repeat steps 6 through 8, changing data and advancing the address counter for the
10. Power-off sequence:
Apply power between VCC and GND pins
Set RST and XTAL1 to GND
Set pin P3.2 to “H”
levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the programming operations
shown in the PEROM Programming Modes table.
cycle is self-timed and typically takes 1.2 ms.
to P3.7 to the appropriate levels. Output data can be read at the port P1 pins.
internal address counter. Apply new data to the port P1 pins.
entire 4K bytes array or until the end of the object file is reached.
set XTAL1 to “L”
set RST to “L”
Turn V
CC
power off
1001F–MICRO–6/08

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