ATTINY461V-10MU Atmel, ATTINY461V-10MU Datasheet - Page 148

• Manufacturer Part Number: ATTINY461V-10MU
• Description: IC MCU AVR 4K FLASH 10MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY461V-10MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: 2-Wire, SPI, USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Package: 32MLF EP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 10 MHz
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.6
148
Changing Channel or Reference Selection
ATtiny261/461/861
Figure 15-7. ADC Timing Diagram, Free Running Conversion
For a summary of conversion times, see
Table 15-1.
The MUX5:0 and REFS2:0 bits in the ADCSRB and ADMUX registers are single buffered
through a temporary register to which the CPU has random access. This ensures that the chan-
nels and reference selection only takes place at a safe point during the conversion. The channel
and reference selection is continuously updated until a conversion is started. Once the conver-
sion starts, the channel and reference selection is locked to ensure a sufficient sampling time for
the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion com-
pletes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC
clock edge after ADSC is written. The user is thus advised not to write new channel or reference
selection values to ADMUX until one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special
care must be taken when updating the ADMUX Register, in order to control which conversion
will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the
ADMUX Register is changed in this period, the user cannot tell if the next conversion is based
on the old or the new settings.
ADMUX can be safely updated in the following ways:
Condition
First conversion
Normal conversions
Auto Triggered conversions
ADC Conversion Time
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Conversion
Sample & Hold
(Cycles from Start of Conversion)
Complete
One Conversion
11
12
Table
13.5
1.5
13
2
15-1.
Next Conversion
1
Sign and MSB of Result
LSB of Result
2
MUX and REFS
Update
3
Sample & Hold
Total Conversion Time (Cycles)
4
13.5
25
13
2588E–AVR–08/10