AT90PWM3-16SQ Atmel, AT90PWM3-16SQ Datasheet - Page 204

• Manufacturer Part Number: AT90PWM3-16SQ
• Description: IC AVR MCU FLASH 8K 32SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM3-16SQ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-SOIC (7.5mm Width)
• Processor Series: AT90PWMx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 27
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• On-chip Dac: 10 bit, 1 Channel
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOICATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATSTK520 - ADAPTER KIT FOR 90PWM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.10.4
204
AT90PWM2/3/2B/3B
USART Control and Status Register C – UCSRC
This bit is available for both USART and EUSART mode.
• Bit 2 – UCSZ2: Character Size
The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits (Char-
acter SiZe) in a frame the Receiver and Transmitter use.
This bit have no effect when the EUSART mode is enabled.
• Bit 1 – RXB8: Receive Data Bit 8
RXB8 is the ninth data bit of the received character when operating with serial frames with nine
data bits. Must be read before reading the low bits from UDR.
When the EUSART mode is enable and configured in 17 bits receive mode, this bit contains the
seventeenth bit (see EUSART section).
• Bit 0 – TXB8: Transmit Data Bit 8
TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDR.
When the EUSART mode is enable and configured in 17 bits transmit mode, this bit contains the
seventeenth bit (See EUSART section).
• Bit 7 – Reserved Bit
This bit is reserved for future use. For compatibilty with future devices, this bit must be written to
zero when USCRC is written.
• Bit 6 – UMSEL: USART Mode Select
This bit selects between asynchronous and synchronous mode of operation.
Table 18-4.
When configured in EUSART mode, the synchronous mode should not be set with Manchester
mode (See EUSART section).
• Bit 5:4 – UPM1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Bit
Read/Write
Initial Value
UMSEL
0
1
UMSEL Bit Settings
R/W
7
0
-
UMSEL0
R/W
6
0
Mode
Asynchronous Operation
Synchronous Operation
UPM1
R/W
5
0
UPM0
R/W
4
0
USBS
R/W
3
0
UCSZ1
R/W
2
1
UCSZ0
R/W
1
1
UCPOL
R/W
0
0
4317J–AVR–08/10
UCSRC