PIC12C671T-04E/SM Microchip Technology, PIC12C671T-04E/SM Datasheet - Page 14

• Manufacturer Part Number: PIC12C671T-04E/SM
• Description: IC MCU OTP 1KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C671T-04E/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

PIC12C67X
TABLE 4-1:
DS30561B-page 14
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Note 1: These registers can be addressed from either bank.
Address
Bank 1
(1)
(1)
(1)
(1)
(1,2)
(1)
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC12C67X; always maintain these bits clear.
5: The SCL (GP7) and SDA (GP6) bits are unimplemented on the PIC12C671/672 and read as ’0’.
INDF
OPTION
PCL
STATUS
FSR
TRIS
PCLATH
INTCON
PIE1
PCON
OSCCAL
ADCON1
Shaded locations are unimplemented, read as ‘0’.
tents are transferred to the upper byte of the program counter.
Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY (CONT.)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect data memory address pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
GPPU
IRP
CAL3
Bit 7
GIE
—
—
—
—
—
(4)
INTEDG
RP1
CAL2
PEIE
ADIE
Bit 6
—
—
—
—
(4)
GPIO Data Direction Register
T0CS
CAL1
Bit 5
T0IE
RP0
—
—
—
—
Write Buffer for the upper 5 bits of the PC
T0SE
CAL0
INTE
Bit 4
TO
—
—
—
CALFST
GPIE
Bit 3
PSA
PD
—
—
—
CALSLW
PCFG2
Bit 2
T0IF
PS2
—
—
Z
PCFG1
Bit 1
INTF
POR
PS1
DC
—
—
1999 Microchip Technology Inc.
PCFG0
GPIF
Bit 0
PS0
—
—
—
C
1111 1111
0001 1xxx
--11 1111
---0 0000
-0-- ----
---- --0-
0111 00--
---- -000
0000 0000
0000 0000
xxxx xxxx
0000 000x
Power-on
Value on
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000 0000
1111 1111
0000 0000
000q quuu
uuuu uuuu
--11 1111
---0 0000
0000 000u
-0-- ----
---- --u-
uuuu uu--
---- -000
Resets
Value on
all other
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(3)