ATTINY45-20PU Atmel, ATTINY45-20PU Datasheet
ATTINY45-20PU
Specifications of ATTINY45-20PU
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ATTINY45-20PU Summary of contents
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... Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator • I/O and Packages – Six Programmable I/O Lines – 8-pin PDIP, 8-pin SOIC, 20-pad QFN/MLF, and 8-pin TSSOP (only ATtiny45/V) • Operating Voltage – 1.8 - 5.5V for ATtiny25V/45V/85V – 2.7 - 5.5V for ATtiny25/45/85 • ...
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... As inputs, Port B pins that are externally pulled low will source current if the pull-up ATtiny25/45/85 2 PDIP/SOIC/TSSOP 1 8 VCC 2 7 PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2 PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1) GND 4 5 PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0) NOTE: TSSOP only for ATtiny45/V QFN/MLF 1 15 VCC 2 14 PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2 DNC DNC 4 12 DNC PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1) 5 ...
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The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny25/45/85 as listed in “Alternate Functions ...
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Overview The ATtiny25/45/ low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to ...
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... Reset. ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface conventional non-volatile memory programmer On-chip boot code running on the AVR core ...
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... About 3.1 Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation ...
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Register Summary Address Name Bit 7 0x3F SREG I 0x3E SPH – 0x3D SPL SP7 0x3C Reserved 0x3B GIMSK – 0x3A GIFR – 0x39 TIMSK – 0x38 TIFR – 0x37 SPMCSR – 0x36 Reserved 0x35 MCUCR BODS 0x34 MCUSR ...
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Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI ...
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Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...
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Mnemonics Operands ROR Rd Rotate Right Through Carry ASR Rd Arithmetic Shift Right SWAP Rd Swap Nibbles BSET s Flag Set BCLR s Flag Clear BST Rr, b Bit Store from Register to T BLD Rd, b Bit load from ...
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... For Speed vs see CC 4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa- tion and minimum quantities. 5. For Typical and Electrical characteristics for this device please consult Appendix A, ATtiny25/V Specification at 105°C. ...
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... Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) ATtiny25/45/85 12 (1) Ordering Code Package ATtiny45V-10PU 8P3 ATtiny45V-10SU 8S2 ATtiny45V-10SH 8S2 ATtiny45V-10XU 8X ATtiny45V-10XUR 8X ATtiny45V-10MU 20M1 ATtiny45-20PU 8P3 ATtiny45-20SU 8S2 ATtiny45-20SH 8S2 ATtiny45-20XU 8X ATtiny45-20XUR 8X ATtiny45-20MU 20M1 168. Package Type (2) Operational Range Industrial (4) (-40° ...
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... All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard- ous Substances (RoHS). 3. For Speed vs see CC 4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa- tion and minimum quantities. 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S2 8-lead, 0.200" ...
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Packaging Information 7.1 8P3 Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured ...
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... Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. Package Drawing Contact: packagedrawings@atmel.com 2586M–AVR–07/ ...
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S8S1 Top View e Side View L End View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc. 2325 Orchard Parkway San Jose, CA 95131 R ATtiny25/45/ ...
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Top View e Side View Note: These drawings are for general information only. Refer to JEDEC Drawing MO-153AC. 2325 Orchard Parkway San Jose, CA 95131 R 2586M–AVR–07/ ...
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D 1 Pin TOP VIEW D2 Pin #1 Notch (0. BOTTOM VIEW Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. Note: 2325 Orchard Parkway San Jose, CA 95131 R ATtiny25/45/85 18 ...
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Errata 8.1 Errata ATtiny25 The revision letter in this section refers to the revision of the ATtiny25 device. 8.1.1 Rev D and E No known errata. 8.1.2 Rev B and C • EEPROM read may fail at low supply ...
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... Errata ATtiny45 The revision letter in this section refers to the revision of the ATtiny45 device. 8.2.1 Rev F and G No known errata 8.2.2 Rev D and E • EEPROM read may fail at low supply voltage / low clock frequency 1. EEPROM read may fail at low supply voltage / low clock frequency Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data ...
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Similarly, if supply voltage can not be raised above 2V then operating fre- quency should be more than 2 MHz. This feature is known to be temperature dependent but it has not been characterised. Guidelines are given ...
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When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code. Problem Fix/Work around Do not set Lock Bit Protection Mode 3 when the application code needs to read ...
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Errata ATtiny85 The revision letter in this section refers to the revision of the ATtiny85 device. 8.3.1 Rev B and C No known errata. 8.3.2 Rev A • EEPROM read may fail at low supply voltage / low clock ...
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... Bandgap Voltage vs Section 6.1 “ATtiny25” on page 11 and Section 6.2 “ATtiny45” on page 12 “Features” on page 1, removed Preliminary from ATtiny25 Section 8.4.2 “Code Example” on page 46 “PCMSK – Pin Change Mask Register” on page “TCCR1 – Timer/Counter1 Control Register” on page 92 Timer/Counter1 Control Register” ...
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... COM0B[1:0]: Compare Match Output B Mode” on page 80 “Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source” on page 142 “SPMCSR – Store Program Memory Control and Status Register” on page “Errata ATtiny25” on page 19 “Errata ATtiny45” on page 20 = 3V)” on page 189 CC = 5V)” on page 190 CC = 3V)” ...
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... ATtiny25/45/85 26 “Errata ATtiny85” on page 23 “ATtiny25” on page 11 “ATtiny45” on page 12 “ATtiny85” on page 13 “S8S1” on page 16 “ATtiny25” on page 11 Updated “Low Power Consumption” on page Updated description of instruction length in Updated Flash size in “In-System Re-programmable Flash Program Memory” on page 15 ...
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Rev. 2586I-09/ 10. 11. 12. 13. 9.6 Rev. 2586H-06/ 2586M–AVR–07/10 Updated bit R/W descriptions in: ...
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... Updated values in “DC Characteristics” on page Updated “Register Summary” on page Updated “Ordering Information” on page Updated Rev B and C in “Errata ATtiny45” on page All references to power-save mode are removed. Updated Register Adresses. Updated “Features” on page 1. Updated Figure 1-1 on page 2 ...
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Rev. 2586B-05/ 9.13 Rev. 2586A-02/05 Initial revision. 2586M–AVR–07/10 CLKI added, instances of EEMWE/EEWE renamed EEMPE/EEPE, removed some TBD. Removed “Preliminary Description” from Updated “Features” on page 1. Updated Figure 1-1 ...
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