PIC12C671-04/P Microchip Technology, PIC12C671-04/P Datasheet - Page 64

• Manufacturer Part Number: PIC12C671-04/P
• Description: IC MCU OTP 1KX14 A/D 8DIP
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C671-04/P

• Program Memory Type: OTP
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 8-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: PIC12C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 1
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 4-ch x 8-bit
• Data Rom Size: 128 B
• Height: 3.3 mm
• Length: 9.27 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12C67X
9.5.1
An overflow (FFh
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>)
(INTCON<2>) will be set, regardless of the state of the
enable bits. If used, this flag must be cleared in software.
9.5.2
External interrupt on GP2/INT pin is edge triggered;
either rising if bit INTEDG (OPTION<6>) is set, or fall-
ing, if the INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 9.8 for details on SLEEP mode.
9.5.3
An input change on GP3, GP1 or GP0 sets flag bit GPIF
(INTCON<0>). The interrupt can be enabled/disabled by
setting/clearing
(Section 5.1) . This flag bit GPIF (INTCON<0>) will be
set, regardless of the state of the enable bits. If used, this
flag must be cleared in software.
EXAMPLE 9-1:
EXAMPLE 9-2:
DS30561B-page 64
MOVWF
SWAPF
BCF
MOVWF
:
:(ISR)
:
SWAPF
MOVWF
SWAPF
SWAPF
RETFIE
MOVWF
MOVF
MOVWF
:
:(ISR)
:
MOVF
MOVWF
SWAPF
SWAPF
RETFIE
TMR0 INTERRUPT
INT INTERRUPT
GPIO INTCON CHANGE
on
the
(Section 7.0).
enable
W_TEMP
STATUS,W
STATUS,RP0
STATUS_TEMP
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
W_TEMP
STATUS,W
STATUS_TEMP
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
(0x20 - 0x6F)
SAVING STATUS AND W REGISTERS USING GENERAL PURPOSE RAM
SAVING STATUS AND W REGISTERS USING SHARED RAM (0x70 - 0x7F)
00h) in the TMR0 register will set
GP2/INT
bit
The
pin,
GPIE
flag
flag
(INTCON<3>)
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;Change to bank zero, regardless of current bank
;Save status to bank zero STATUS_TEMP register
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
;Return from interrupt
;Copy W to TEMP register (bank independent)
;Move STATUS register into W
;Save contents of STATUS register
;Retrieve copy of STATUS register
;Restore pre-isr STATUS register contents
;
;Restore pre-isr W register contents
;Return from interrupt
bit
bit
INTF
T0IF
9.6
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt (i.e., W register and STATUS
register). This will have to be implemented in software.
Example 9-1 shows the storing and restoring of the
STATUS and W registers. The register, W_TEMP, must
be defined in both banks and must be defined at the
same offset from the bank base address (i.e., if
W_TEMP is defined at 0x20 in bank 0, it must also be
defined at 0xA0 in bank 1).
Example 9-2 shows the saving and restoring of STA-
TUS and W using RAM locations 0x70 - 0x7F.
W_TEMP is defined at 0x70 and STATUS_TEMP is
defined at 0x71.
The example:
a)
b)
c)
d)
e)
f)
Stores the W register.
Stores the STATUS register in bank 0.
Executes the ISR code.
Restores the STATUS register (and bank select
bit).
Restores the W register.
Returns from interrupt.
Context Saving During Interrupts
1999 Microchip Technology Inc.