PIC12C672-04I/P Microchip Technology, PIC12C672-04I/P Datasheet - Page 209

• Manufacturer Part Number: PIC12C672-04I/P
• Description: IC MCU OTP 2KX14 A/D 8DIP
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672-04I/P

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Ram Memory Size: 128Byte
• Cpu Speed: 4MHz
• No. Of Timers: 1
• Digital Ic Case Style: DIP
• Processor Series: PIC12C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 1
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

14.4.1
14.4.2
14.4.3
14.4.4
14.4.5
1997 Microchip Technology Inc.
CCP Pin Operation in Compare Mode
Software Interrupt Mode
Special Event Trigger
Sleep Operation
Effects of a Reset
The user must configure the CCPx pin as an output by clearing the appropriate TRIS bit.
Selecting the compare output mode, forces the state of the CCP pin to the state that is opposite
of the match state. So if the Compare mode is selected to force the output pin low on match, then
the output will be forced high until the match occurs (or the mode is changed).
When generate Software Interrupt mode is chosen, the CCPx pin is not affected. Only a CCP
interrupt is generated (if enabled).
In this mode, an internal hardware trigger is generated which may be used to initiate an action.
The special event trigger output of CCPx resets the TMR1 register pair. This allows the CCPRx
register to effectively be a 16-bit programmable period register for Timer1.
For some devices, the special trigger output of the CCP module resets the TMR1 register pair,
and starts an A/D conversion (if the A/D module is enabled).
When the device is placed in sleep, Timer1 will not increment (since in synchronous mode), and
the state of the module will not change. If the CCP pin is driving a value, it will continue to drive
that value. When the device wakes-up, it will continue form this state.
The CCP module is off.
Note:
Note:
Clearing the CCPxCON register will force the CCPx compare output latch to the
default low level. This is not the Port I/O data latch.
The special event trigger will not set the Timer1 interrupt flag bit, TMR1IF.
Section 14. CCP
DS31014A-page 14-7
14