PIC18F45J10-I/ML Microchip Technology, PIC18F45J10-I/ML Datasheet - Page 2

• Manufacturer Part Number: PIC18F45J10-I/ML
• Description: IC PIC MCU FLASH 16KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F45J10-I/ML

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC18
• No. Of I/o's: 21
• Ram Memory Size: 1024Byte
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Interface: I2C, SPI, USART
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163022, DM183040
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNAC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PXLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F24J10/25J10/44J10/45J10
6. Module: MSSP
7. Module: MSSP (I
DS80380A-page 2
In SPI mode, the Buffer Full flag bit, BF
(SSPxSTAT<0>), the Write Collision Detect bit,
WCOL (SSPxCON1<7>), and the Receive Overflow
Indicator bit, SSPOV (SSPxCON1<6>), are not
reset upon disabling the SPI module (by clearing
the SSPEN bit in the SSPxCON1 register).
For example, if SSPxBUF is full (BF bit is set) and
the MSSP module is disabled and re-enabled, the
BF bit will remain set. In SPI Slave mode, a sub-
sequent write to SSPxBUF will result in a write
collision. Also, if a new byte is received, a receive
overflow will occur.
Work around
Ensure that if the buffer is full, SSPxBUF is read
(thus, clearing the BF flag) and WCOL is clear
before disabling the MSSP module. If the module
is configured in SPI Slave mode, ensure that the
SSPOV bit is clear before disabling the module.
It has been observed that following a Power-on
Reset, I
configuring the SCLx and SDAx pins as either
inputs or outputs. This has only been seen in a few
unique system environments.
A test of a statistically significant sample of pre-
production systems, across the voltage and
current range of the application’s power supply,
should indicate if a system is susceptible to this
issue.
Work around
Before configuring the module for I
1. Configure the SCLx and SDAx pins as outputs
2. Force SCLx and SDAx low by clearing the
3. While keeping the LAT bits clear, configure
Once this is done, use the SSPxCON1 and
SSPxCON2 registers to configure the proper I
mode as before .
by clearing their corresponding TRIS bits.
corresponding LAT bits.
SCLx and SDAx as inputs by setting their TRIS
bits.
2
C mode may not initialize properly by just
2
C™ Mode)
2
C operation:
2
C
8. Module: Core (Program Memory Space)
9. Module: EUSART
Writes to program memory address 300000h, that
are not blocked, can cause the program memory
at different locations to be corrupted.
Work around
Do not write to address 300000h. If you wish to
modify the contents of the Configuration registers,
then modify the Configuration Words located at the
end of the user memory (7FF4h for PIC18FX5J10
devices and 3FF4h for PIC18FX4J10 devices) and
issue a Reset command. This will reload the
Configuration registers with the new configuration
setting.
In rare situations, one or more extra zero bytes
have been observed in a packet transmitted by the
module operating in Asynchronous mode. The
actual data is not lost or corrupted; only unwanted
(extra) zero bytes are observed in the packet.
This situation has only been observed when the
contents of the transmit buffer, TXREG, are trans-
ferred to the TSR during the transmission of a Stop
bit. For this to occur, three things must happen in
the same instruction cycle:
• TXREG is written to;
• the baud rate counter overflows (at the end of
• a Stop bit is being transmitted (shifted out of
Work around
If possible, do not use the module’s double-buffer
capability. Instead, load the TXREG register when
the TRMT bit (TXSTA<1>) is set, indicating the
TSR is empty.
If double-buffering is used and back-to-back
transmission is performed, then load TXREG
immediately after TXIF is set or wait 1-bit time after
TXIF is set. Both solutions prevent writing TXREG
while a Stop bit is transmitted. Note that TXIF is set
at the beginning of the Stop bit transmission.
If transmission is intermittent, then do the
following:
Date Codes that pertain to this issue:
All engineering and production devices.
the bit period); and
TSR).
• Wait for the TRMT bit to be set before
• Alternatively, use a free timer resource to
loading TXREG.
time the baud period. Set up the timer to
overflow at the end of the Stop bit, then start
the timer when you load the TXREG. Do not
load the TXREG when timer is about to
overflow.
© 2008 Microchip Technology Inc.