PIC18F65J10-I/PT Microchip Technology, PIC18F65J10-I/PT Datasheet - Page 5

• Manufacturer Part Number: PIC18F65J10-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J10-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11. Module: EUSART
© 2006 Microchip Technology Inc.
In rare situations, one or more extra zero bytes
have been observed in a packet transmitted by the
module operating in Asynchronous mode. The
actual data is not lost or corrupted; only unwanted
(extra) zero bytes are observed in the packet.
This situation has only been observed when the
contents of the transmit buffer, TXREGx, are trans-
ferred to the TSR during the transmission of a Stop
bit. For this to occur, three things must happen in
the same instruction cycle:
• TXREGx is written to;
• the baud rate counter overflows (at the end of
• a Stop bit is being transmitted (shifted out of
Work around
If possible, do not use the module’s double-buffer
capability. Instead, load the TXREGx register
when the TRMT bit (TXSTAx<1>) is set, indicating
the TSR is empty.
If double-buffering is used and back-to-back
transmission is performed, then load TXREGx
immediately after TXxIF is set, or wait 1-bit time
after TXxIF is set. Both solutions prevent writing
TXREGx while a Stop bit is transmitted. Note that
TXxIF is set at the beginning of the Stop bit
transmission.
If transmission is intermittent, then do the
following:
Date Codes that pertain to this issue:
All engineering and production devices.
the bit period); and
TSR).
• Wait for the TRMT bit to be set before
• Alternatively, use a free timer resource to
loading TXREGx.
time the baud period. Set up the timer to
overflow at the end of Stop bit, then start the
timer when you load the TXREGx. Do not
load the TXREGx when timer is about to
overflow.
PIC18F87J10 FAMILY
12. Module: EUSART
13. Module: EUSART
14. Module: EUSART
Note:
In 9-Bit Asynchronous Full-Duplex Receive mode,
the received data may be corrupted if the TX9D bit
(TXSTAx<0>) is not modified immediately after the
RCIDL bit (BAUDCONx<6>) is set.
Work around
Write to TX9D only when a reception is not in
progress (RCIDL = 1). Since there is no interrupt
associated with RCIDL, it must be polled in software
to determine when TX9D can be updated.
Date Codes that pertain to this issue:
All engineering and production devices.
After the last received byte has been read from the
EUSART receive buffer, RCREGx, the value is no
longer valid for subsequent read operations.
Work around
The RCREGx register should only be read once for
each byte received. After each byte is received from
the EUSART, store the byte into a user variable. To
determine when a byte is available to read from
RCREGx, poll the RCIDL bit (BAUDCONx<6>) for
a low-to-high transition, or use the EUSART
Receive Interrupt Flag, RC1IF (PIR1<5>).
Date Codes that pertain to this issue:
All engineering and production devices.
With the auto-wake-up option enabled by setting
the WUE bit (BAUDCONx<1>), the RC1IF
(PIR1<5>) bit will become set on a high-to-low
transition on the RXx pin. While the WUE bit is set,
reading the receive buffer, RCREGx, will not clear
the RCxIF interrupt flag. Therefore, the first oppor-
tunity to automatically clear RCxIF by reading
RCREGx will happen only after WUE bit is cleared.
Work around
There are two workarounds available:
1. Poll the WUE bit and read RCREGx after the
Date Codes that pertain to this issue:
All engineering and production devices.
WUE bit is automatically cleared.
RCxIF can only be cleared by reading
RCREGx
DS80246B-page 5