PIC16LC715-04I/SS Microchip Technology, PIC16LC715-04I/SS Datasheet - Page 13

• Manufacturer Part Number: PIC16LC715-04I/SS
• Description: IC MCU OTP 2KX14 A/D PWM 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC715-04I/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Core: PIC
• Processor Series: PIC16LC
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 128 B
• Data Rom Size: 128 B
• On-chip Adc: 4 bit
• Number Of Programmable I/os: 13
• Number Of Timers: 1
• Operating Supply Voltage: 2.5 V to 6 V
• Mounting Style: SMD/SMT
• Height: 1.75 mm
• Length: 7.2 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 6 V
• Supply Voltage (min): 4 V
• Width: 5.3 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

FIGURE 4-5:
1997 Microchip Technology Inc.
Note 1: Not a physical register.
Address
0Ch
0Ah
0Bh
4Fh
7Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
50h
File
2: These locations are unimplemented in Bank 1.
Unimplemented data memory locations, read
as '0'.
Any access to these locations will access the
corresponding Bank 0 register.
ADCON0
PCLATH
INTCON
Purpose
STATUS
Register
General
PORTB
ADRES
INDF
PORTA
Bank 0
TMR0
FSR
PCL
PIC16C711 REGISTER FILE
MAP
(1)
in Bank 0
ADCON1
Purpose
Register
OPTION
PCLATH
INTCON
General
Mapped
STATUS
ADRES
Bank 1
INDF
TRISA
TRISB
PCON
FSR
PCL
(1)
(2)
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
CFh
D0h
FFh
File
FIGURE 4-6:
Note 1: Not a physical register.
Address
File
0Ch
0Dh
1Ch
1Dh
0Ah
0Bh
0Eh
1Ah
1Bh
1Eh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Fh
20h
7Fh
Unimplemented data memory locations, read
as '0'.
ADCON0
PCLATH
INTCON
STATUS
PORTB
ADRES
INDF
PORTA
Bank 0
TMR0
PIR1
Purpose
Register
General
PCL
FSR
PIC16C715 REGISTER FILE
MAP
(1)
PIC16C71X
ADCON1
Purpose
Register
OPTION
PCLATH
INTCON
General
STATUS
INDF
Bank 1
TRISA
TRISB
PCON
PIE1
PCL
FSR
DS30272A-page 13
(1)
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BFh
C0h
FFh
File