AT90USB162-16MU Atmel, AT90USB162-16MU Datasheet - Page 174

• Manufacturer Part Number: AT90USB162-16MU
• Description: MCU AVR USB 16K FLASH 32-QFN
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB162-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, PS/2, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFN
• Controller Family/series: AVR USB
• No. Of I/o's: 22
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Processor Series: AT90USBx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART, debugWIRE
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATSTK526, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK526 - KIT STARTER FOR AT90USB82/162ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

18.2
Table 18-1.
174
Operating Mode
Synchronous Master mode
Clock Generation
AT90USB82/162
Equations for Calculating Baud Rate Register Setting
control logic is disabled. The USART RX and TX control logic is replaced by a common SPI
transfer control logic. However, the pin control logic and interrupt generation logic is identical in
both modes of operation.
The I/O register locations are the same in both modes. However, some of the functionality of the
control registers changes when using MSPIM.
The Clock Generation logic generates the base clock for the Transmitter and Receiver. For
USART MSPIM mode of operation only internal clock generation (i.e. master operation) is sup-
ported. The Data Direction Register for the XCKn pin (DDR_XCKn) must therefore be set to one
(i.e. as output) for the USART in MSPIM to operate correctly. Preferably the DDR_XCKn should
be set up before the USART in MSPIM is enabled (i.e. TXENn and RXENn bit set to one).
The internal clock generation used in MSPIM mode is identical to the USART synchronous mas-
ter mode. The baud rate or UBRRn setting can therefore be calculated using the same
equations, see
Note:
BAUD
f
UBRRn
OSC
1. The baud rate is defined to be the transfer rate in bit per second (bps)
Equation for Calculating Baud Rate
BAUD
Table
18-1:
=
Baud rate (in bits per second, bps)
System Oscillator clock frequency
Contents of the UBRRnH and UBRRnL Registers, (0-4095)
-------------------------------------- -
2 UBRRn
(
f
OSC
+
1
)
(1)
Equation for Calculating UBRRn Value
UBRRn
=
------------------- - 1
2BAUD
f
OSC
–
7707F–AVR–11/10