PIC16C642-04/SO Microchip Technology, PIC16C642-04/SO Datasheet - Page 20

IC MCU OTP 4KX14 COMP 28SOIC

PIC16C642-04/SO

Manufacturer Part Number
PIC16C642-04/SO
Description
IC MCU OTP 4KX14 COMP 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets

Specifications of PIC16C642-04/SO

Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Core Processor
PIC
Speed
4MHz
Peripherals
Brown-out Detect/Reset, LED, POR, WDT
Number Of I /o
22
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
PIC16C
No. Of I/o's
22
Ram Memory Size
176Byte
Cpu Speed
4MHz
No. Of Timers
1
Processor Series
PIC16C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
176 B
Interface Type
RS- 232
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
33
Number Of Timers
8
Operating Supply Voltage
3 V to 6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000, DM163022
Minimum Operating Temperature
0 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
 Details
PIC16C64X & PIC16C66X
TABLE 4-1:
DS30559A-page 20
Address Name
Bank 0
00h
01h
02h
03h
04h
06h
06h
06h
06h
0Ah
0Bh
0Ch
0Dh-1Eh Unimplemented
1Fh
Bank 1
80h
81h
82h
83h
84h
86h
86h
86h
86h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh-9Eh Unimplemented
9Fh
Note
05h
85h
Legend: - = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
1: Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: The IRP and RP1 bits are reserved, always maintain these bits clear.
3: The PORTD, PORTE, TRISD, and TRISE registers are not implemented on the PIC16C641/642.
4: Bits PSPIE and PSPIF are reserved on the PIC16C641/642, always maintain these bits clear.
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
CMCON
INDF
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
Unimplemented
PCON
VRCON
(3)
(3)
(3)
(3)
SPECIAL FUNCTION REGISTERS
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
Timer0 Module’s Register
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
PSPIF
PSPIE
MPEEN
C2OUT
RBPU
VREN
IRP
IRP
Bit 7
GIE
GIE
IBF
(2)
(2)
(4)
(4)
INTEDG
C1OUT
RP1
RP1
VROE
CMIE
CMIF
PEIE
PEIE
Bit 6
OBF
(2)
(2)
PORTA Data Latch when written: PORTA pins when read
PORTA Data Direction Register
T0CS
IBOV
Bit 5
T0IE
T0IE
VRR
RP0
RP0
Preliminary
Write buffer for upper 5 bits of program counter
Write buffer for upper 5 bits of program counter
PSPMODE
T0SE
INTE
INTE
Bit 4
TO
TO
RBIE
RBIE
Bit 3
PSA
VR3
CIS
PD
PD
TRISE2
Bit 2
CM2
RE2
T0IF
T0IF
PER
VR2
PS2
Z
Z
TRISE1
INTF
INTF
POR
Bit 1
CM1
RE1
PS1
VR1
DC
DC
1996 Microchip Technology Inc.
TRISE0
RBIF
RBIF
BOR
Bit 0
CM0
RE0
PS0
VR0
C
C
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--xx 0000 --xu 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
---0 0000 ---0 0000
0000 000x 0000 000u
00-- ---- 00-- ----
00-- 0000 00-- 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
0000 -111 0000 -111
---0 0000 ---0 0000
0000 000x 0000 000x
00-- ---- 00-- ----
u--- -qqq u--- -uuu
000- 0000 000- 0000
Value on
BOR,
POR,
PER
Value on
all other
resets
(1)

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